臺灣博碩士論文加值系統

隨著穿戴式裝置與物聯網的興起，低功耗且高密度的靜態隨機存取記憶體(Static Random Access Memory, SRAM)的需求日益加。降低操作電壓和改用先進製程是降低功耗的有效方式。但隨著製程尺寸的微縮，載子參雜濃度加重使得晶片的變異更加嚴重，微縮的尺寸也造成了漏電流增大，驅動力變小，種種因素使得6T SRAM工作時發生錯誤的機率提高，使6T SRAM設計面臨更大的考驗。為了維持傳統6T SRAM具有高密度與雙端讀取的優勢，分別出現了讀與寫的輔助電路(Read and Write assist circuits)，降低傳統SRAM在低電壓或先進製程下發生錯誤的機率，使6T SRAM得以往更低操作電壓、更先進製程發展。
論文接著討論讀和寫輔助電路搭配交錯式排列結構陣列面臨的問題，與輔助電路的演進，最後整理輔助電路組合的優勢和劣勢。
為了解決過去輔助電路的問題，本論文提出2個新的於28nm具有變異抵抗能力且低功耗之輔助電路(assist circuits)。Read assist circuits利用電晶體特性結合字線驅動器(Word-line driver)電路與降漏電流電路，完成具變異容忍之字線降壓技術(Variation Tolerance Suppress Wordline, vtsWL)。且使用電路設計方式解決了過去sWL技術直流耗電造成的功率消耗。本文提出之新讀的輔助電路節省了過去讀輔助電路的11倍。Write assist circuits使用細胞元供電電壓降壓技術(VCC Lower, VCCL)搭配回授機制，產生對變異具容忍度的VCCL，且本文提出之VCCL比起過去VCCL電路節省了將近一半的功率消耗。

With the rise of wearable devices and Internet of Things, the demand for low-power and high-density static random access memory (SRAM) is increasing. Reducing the operating voltage and switching to advanced processes is an effective way to reduce power consumption. However, as the size of the process shrinks, the carrier concentration increases so that the variation of the wafer is more serious, the shrinking size also causes the leakage current to increase and the driving current becomes smaller. Various factors make the chance of 6T SRAM function error, so that 6T SRAM design is facing a greater challenges. In order to maintain the traditional 6T SRAM with high density and high speed the advantages of read and write access to the assist circuit. The assists circuit reduces the chance that traditional SRAM will be erroneous in low voltage or advanced processes. So that 6T SRAM can be lower operating voltage, more advanced process development.
Then discusses the problems faced by the read and write assists circuit with the interleaving array structure, the evolution of the assists circuit, and the advantages and disadvantages of the assists circuit combination.
In order to solve the problem of assists circuits in the past, this paper proposes two new assists with 28 nm variability toleration and low power consumption. Read assists circuits uses the transistor characteristics to combine the word-line driver circuit with the reduced leakage current circuit to complete the Variation Tolerance Suppress Wordline (vtsWL). This paper proposed a new reading of the assists circuit to save the past read assists circuit 11 times. VCC Lower with the feedback mechanism to produce VCCL with variation tolerance, and VCCL proposed in this paper saves nearly half the power consumption compared to the past VCCL circuit.

摘要 I
Abrtract II
目錄 IV
圖目錄 V
表目錄 VIII
第一章 序論 1
1.1 研究背景 1
1.2 研究動機 2
1.3 論文架構 4
第二章 記憶體輔助電路介紹 5
2.1 Suppress Bitline 6
s2.2 Suppress Wordline 8
2.3 Read Assist Technique comparison 18
2.4 Boost WL 19
2.5 Negative Bitline 22
2.6 VCC Lower 24
2.7 Write Assist Technique comparison 28
第三章 Proposed Read and Write Assist Circuits 29
3.1 Variation Tolerance Suppress Wordline 29
3.2 Feedback Control VCC Lower 34
第四章 輔助電路比較(與pre-simulation) 37
第五章 未來研究方向 41
參考文獻 42

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