臺灣博碩士論文加值系統

本論文主要分為兩大電路，一為寬頻CMOS混頻器，一為高頻類比數位轉換器，分兩個部分詳細介紹。
第一部分為應用於微波接收機之0.18um-CMOS寬頻混頻器，將17.4-26.1GHz之訊號降至DC-8.7GHz。此電路包含RF低雜訊放大器、寬頻混頻器、IF放大級、本地震盪倍頻器、以及偏壓電路。第二部分介紹高頻類比數位轉換器雛型電路，將接收之類比高頻訊號轉為數位輸出。包含取樣電路、前置放大器、比較器、以及編碼器。
將兩部分的電路合在一起以期能擴大系統，直接將高頻訊號降頻接至數位輸出，但數位輸出部分受限於頻寬和可解析的訊號大小，還有很大的改進空間。

This thesis discusses two circuit designs. One is a wideband CMOS receiver, and the other is a RF-to-digital converter.
The 0.18um-CMOS, 17-26 GHz (K-band) receiver contains RF LNA, wideband mixer, IF amplifier, and LO frequency doubler. The circuit architecture, simulation results, chip layout and measured results are presented. The conversion gain of mixer is 0 dB. The IF-RF isolation is 40 dB.
The RF-to-digital converter consists of sample-and-hold circuit, preamplifier, comparator, and encoder. The circuit architecture, simulation results and 90nm-CMOS and 0.18-CMOS layouts are discussed.

目錄
中文提要 i
英文提要 ii
誌謝 iii
目錄 iv
圖目錄 vii
第一章 緒論 1
1.1 研究動機 1
1.2 論文架構 2
第二章 寬中帶微波CMOS混頻器 3
2.1 引言 3
2.2 Marchand balun 4
2.3 RF 放大級電路 8
2.4 混頻器 10
2.5 IF 放大級電路 11
2.6 本地震盪倍頻器 14
2.7 電路佈局及量測結果 18
第三章 高頻類比數位轉換器 23
3.1 引言 23
3.2 高頻類比數位轉換器架構 24
3.3 取樣電路 26
3.4 比較器 27
3.5 模擬結果 28
3.3 電路佈局 30
第四章 能隙參考（位準偏壓）電路 31
4.1 引言 31
4.2 架構原理及模擬結果 31
4.3 電路佈局與量測結果 33
第五章 結論 34
5.1 結論 34
5.2 未來展望 34
參考文獻 35

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