臺灣博碩士論文加值系統

本論文研究在厚層印刷電路板(PCB)中對於時域傳輸波形TDT (Time -Domain Transmission)與眼圖的影響，同時提出對於降低最長的差模連通柱殘段的影響之抑制方案，使用彈跳圖(Lattice Diagram)可以得知時域反射雜訊影響到時域傳輸波形主要是最長的差模訊號連通柱殘段所造成的影響，接著利用彈跳圖(Lattice Diagram) 推導公式用於計算時域傳輸波形波形之步階電壓高度，接下來分析最長的差模連通柱殘段影響時域傳輸波形之參數變化，且對於最長的差模連通柱殘段造成的影響提出了高阻抗差異比與有無嵌入額外空氣連通柱之抑制方案，所提出之抑制方案不管是在時域傳輸波形與眼圖或是頻域差模介入損失|Sdd21|皆大幅抑制了在厚層印刷電路板中最長的差模訊號連通殘段對訊號造成的影響，最後模擬與量測不管在時域或是頻域上皆有很好的一致性，驗證了本論文的分析與所提出的抑制方案是可行的。

This study investigates how the longest differential via stubs in a thick multilayered printed circuit board (PCB) affect the time-domain transmission (TDT) waveform and eye diagram. A reduction scheme is also proposed to mitigate the influence of the longest differential via stubs. The manner in which the time-domain reflection noise that is generated by the longest differential via stubs affects the TDT waveform is then investigated using a lattice diagram. Formulas for step voltages on the TDT waveform are derived by analyzing the lattice diagram. Next, the effects of parameters related to the longest differential via stubs on the TDT waveform are analyzed. A high-impedance difference scheme with/without additional air-via holes is proposed to mitigate the influence of the longest differential via stubs. This mitigation scheme significantly reduces the influence of the longest differential via stubs in a thick multilayered PCB not only in the time domain (TDT waveform and eye diagram) but also in the frequency domain (differential insertion loss |Sdd21|). Finally, favorable comparisons between the simulations and measurements in the time and frequency domains validate the proposed analyses and mitigation scheme.

目錄
摘要....................................................................I
Abstract...............................................................II
致謝....................................................................III
目錄....................................................................V
圖表索引.................................................................VII
第一章簡介...............................................................1
1-1研究動機..............................................................1
1-2文獻回顧與探討.........................................................1
1-3 章節概要.............................................................2
1-4成果貢獻..............................................................3
第二章 傳輸線反射原理......................................................4
2-1反射與傳輸參數.........................................................4
2-2彈跳圖 ................................................................8
第三章 長訊號連通柱殘段對訊號完整性的影響......................................13
3-2對時域傳輸波形波形與眼圖的影響分析.........................................17
3-3相關參數分析...........................................................22
第四章 訊號連通柱殘段效應之抑制..............................................25
4-1高阻抗連通柱殘段之效應抑制概念............................................25
4-2範例抑制效率之分析與比較.................................................26
第五章 實驗驗證...........................................................31
第六章 結論..............................................................35
參考文獻.................................................................36
已發表論文...............................................................38

圖表索引
第二章
圖2-1傳輸線A中的訊號碰到阻抗不連續點時，一部分將反射到訊號源，另一部分將透射到傳輸線B....5
圖2-2 入射訊號遇到不匹配負載反射...............................................6
圖2-3 (A)傳輸線終端阻抗匹配 (B) 傳輸線終端短路 (C) 傳輸線終端開路..................7
圖2-4傳輸線多重反射例子.......................................................8
圖2-5傳輸線的彈跳圖範例.......................................................9
第三章
圖3-1 (A) 差模訊號通孔連通柱典形結構之3D圖 (B)上視圖 (C)側視圖....................14
圖3-2 比較主要結構在不同厚度下的差模介入損耗.....................................15
圖3-3 比較主要結構在不同的板厚與不同資料傳輸速率下模擬眼圖之比較.....................16
(A)與(D)厚度為150MIL (B)與(E)厚度為200MIL (C)與(F)厚度為250MIL...............16
圖3-4 比較有無差模訊號連通柱殘段之時域傳輸波形.....................................17
圖3-5 本論文提出結構之簡化等效電路模型 ...........................................19
圖3-6 (A) Q3D模擬差模訊號連通柱模型 (B) 無損條件下之差模訊號連通柱的簡化等效分佈電路模型的單位元件........................................................................19
圖3-7 分析本論文提出結構之彈跳圖.................................................20
圖3-8 有無差模訊號連通柱殘段近似的時域傳輸波形斜波步階響應的主要部分....................21
圖3-9提出結構比較差模訊號連通柱殘段與金屬平面不同(DVH)下之時域傳輸波形..................22
圖3-10 本論文所提出結構比較不同金屬層層數下之時域傳輸波形.............................23
圖3-11 本論文所提出結構比較不同金屬層層數下之時域傳輸波形.............................24
圖3-12 本論文所提出結構比較差模訊號連通柱之圓心至接地連通柱之圓心不同距離(SGV)下之時域傳輸波形 ............................................................................24
表3-1 幾何結構尺寸及其材料特性...................................................14
表3-2 比較本論文提出結構使用CST模擬與公式計算之差模訊號連通柱殘段造成的時域傳輸波形的步階電壓高度V1、V2與V3與延遲時間的影響。...................................................21
第四章
圖4-1步階電壓V1、V2與V3與阻抗差異比參數K之函數.....................................26
圖4-2 新的降低差模連通柱殘段影響之抑制方案結構上視圖與相對應之參數(A)例子4 (B)例子5......27
圖4-3本論文提出的五個驗證例子各有不同的差模阻抗差異比參數之時域傳輸波形..................28
圖4-4本論文提出的五個驗證例子各有不同的差模阻抗差異比參數之時域傳輸波形..................29
圖4-5五個驗證例子在傳送速率7GHZ下有不同的差模阻抗差異比參數之眼圖......................30
表4-1 列出不同阻抗差異比參數的五個驗證例子.........................................27
第五章
圖5-1 比較量測三種結構與模擬結果之時域傳輸波形......................................33
圖5-2 比較量測三種結構與模擬結果之差模介入損失(|SDD21|)波形..........................34
表5-1 量測結構幾何結構尺寸與板材特性...............................................31

[1]D. Y. Kim, J. Byum, S. H. Lee, S. J. Oh, and H. Y. Lee, “Signal integrity improvements of a MEMS probe card using back-reilling and equalizing techniques,” IEEE Trans. Instrumentatuin and Measurement, vol. 60, no. 3, pp. 872–879, March 2011.
[2]S. H. Hall and H. L. Heck, Advanced Signal Integrity for High-Speed Digital System Design. New York: Wiley, 2009.
[3]T. Kushta, K. Narita, T. Kaneko, T. Saeki, and H. Tohya, “Resonance stub effect in a transition from a through via hole to a stripline in multilayer PCBs,” IEEE Microwave and Wireless Components Letters, vol. 13, no. 5, pp. 169–171, May 2003.
[4]S. Deng, J. Mao, T. H. Hubing, J. L. Drewniak, J. Fan, J.L. Knighten, N. W. Smith, and R. Alexander, “Effects of open stubs associated with plated through-hole vias in backpanel designs,” IEEE Symp. Electromagn. Compat., pp. 1017–1022, Aug. 2004.
[5]J. Shin and, T. Michalka, “Comprehensive design guidance for PTH via stub in board-level high speed differential interconnects,” Electronic Components and Technology Conference, pp. 1912–1919, 2010.
[6]W. Y. Chang, Kye Yak See, and Eng Kee Chua, “Comprehensive analysis of the impact of via design on high-speed signal integrity,” Electronic Packaging Technology Conf., pp. 262–266, 2007.
[7]S. H. Joo, D. Y. Kim, S. H. Lee, S. J. Oh, K. S. Kang, and H. Y. Lee, “Resistively-terminated via-stubs for signal integrity improvement in the semiconductor test board,” Microwave Conference, pp.121-124, Oct. 2007.
[8]C. L. Yeh, Yi. C. Tsai, C. M. Hsu, L. S. Liu, S. H. Tsai, and G. H. Shiue, “Influence of via stubs with different terminations on time-domain transmission waveform and eye diagram in multilayer PCBs,” IEEE Electrical Design of Advanced Packaging and Systems Symposium, pp. 149-152, Dec. 2012.
[9]Y. S. Cheng, H. H. Lu, M. Chang, S. Chang, B. Liu, and R. B. Wu, “SI-aware layout and equalizer design to enhance performance of high-speed links in blade servers,” IEEE Electrical Performance of Electronic Packaging and Systems, pp. 199-202, Oct. 2011.
[10]Ansys HFSS. ver. 13, Ansys, Pittsburgh, PA. [Online]. Available: www.ansys.com.

[11]Advanced design system 2009, Angilent Inc., PA. [Online]. Available: www.home.agilent.com .

[12]S. Pan, and J. Fan,“Equivalent mixed-mode characteristic impedances for differential signal vias,” IEEE Symp. Electromagn. Compat., pp. 74–79, Aug. 2009.
[13]S. Pan, and J. Fan,“Characterization of via structures in multilayer printd circuit boards with an equivalent transmission-line model,” IEEE Tran. Electromagn. Compat., pp. 1077–1086, Oct. 2012.
[14]Q3D. ver. 10, Ansys, Pittsburgh, PA. (2009). [Online]. Available: www.ansys.com.

[15]J. D. Geest, D. Bergey, J. Lynch, D. Miller, and S. Sercu, “Improving system performance by reducing system impedance to 85 ohms,” Design Con, Jan. 2007.