臺灣博碩士論文加值系統

快閃記憶體為非揮發性記憶體之種類，重視之資料保存及容量。傳統非揮發性記憶體採用覆晶系當做浮動閘極材料，由於覆晶矽本身是半導體材料，會有漏電等問題，近幾年來已經發展利用Oxide-nitride-oxide三層取代傳統浮停閘，因本身是絕緣材料,漏電問題較不易呈現,且本身具有深層陷入能階,局部陷入電荷等特性可發展為多位元記憶體。
本論文中嘗試提出一個具有垂直側壁ONO三層堆疊架構分散建構在結構背端於通道下方。該分離垂直式的ONO結構將不會對通道長度的微縮造成侷限，且因槽底此對分離垂直式的ONO結構彼此間有氧化層及某厚度的矽化層做有效隔離，不會有位元間彼此互相干擾。
本論文以此推論探討克服傳統記憶體元件的可行性及發展侷限
提高元件積集密度，使造價便宜而具競爭性。這對未來發展有很大的幫助。

Flash memory is one sort of non-volatile memory, focus on the dates holding and capacity. Conventional non-volatile memory applies poly-crystalline for floating gate material, because the poly-crystalline (like poly-silicon) itself is the semiconductor material, will cause leakage problem, recently, Oxide-nitride-oxide multi-layer structure is under development for the place of conventional floating gate. Because it is the insulator material, can suppress leakage current, and it contains a deeper trapping energy level, and has a partial trapped carriers phenomenon to give a multi-bits memory solution.

My effort is to propose a pair of ONO three layers stack, which is located close to the beneath of D/S region and a column like. Such structure can overcome miniaturization limitation of channel length, and a somewhat depth oxide can promise good isolation and separation between the trapping layer and other area, and a reliable distance of the two trapped unit can prevent interference issue.

My proposal can suppose a higher devices density and a feasible and flexible solution to develop memory devices, a cost down to be more competitive, certainly bring much favor for the future improvement.

第一章 非揮發記憶體(Non-volatile Memory)的簡介 1
1-1非揮發記憶體的發展 1
1-2 floating gate device 4
1-3 MIOS(metal-insulato-oxide-silicon)元件 5
1-4 趨勢發展 6
第二章 SONOS記憶體原理及操作 10
2-1通道熱電子注入(channel hot electron injection)(CHEI)10
2-2FN穿遂(Fowler-Nordheim tunneling) 11
2-3 操做情況 12
2-3-1寫入(programming) 12
2-3-2抹除(erasing) 14
2-3-3讀取(read) 15
2-3-3-1 順向讀出(forward read) 16
2-3-3-2 反向讀出(reverse read) 17
2-4 結論 18
第三章 新元件的模擬 19
3-1簡介 19
3-2 ISE TCAD 模擬製程 19
3-3模擬電性 22
3-3-1 偏壓設定 22
3-3-2 特性曲線模擬 23
3-4結論 31
第四章 元件的設計與製作 32
4-1 製作well BODY 32
4-2 製作ONO stack 38
4-3 定義完成主動區域 39
4-4 沉積閘極氧化層 41
4-5 定義閘極 41
4-6 形成源、汲極區域 44
4-7 製作金Contact Hole 44
4-8 製作金屬層 46
Reference 48
附錄 C: Layout 圖 51

[1]DOV FROHMAN-BENTCHKOWSKY.” “A Fully Decoded 2048-Bit Electrically Programmable FAMOS Read-Only Memory” IEEE JOURNAL OF SOLID-STATCEIRCUITSV,OL.SC-6,NO.5,OCTOBER1971
[2]Tom Wett, Stuart Levy Intel Corporation .” Flash - The Memory Technology of the Future That''s Here Today” Military and Special Products Division Technical Marketing Engineers 5000 W, Chandler Blvd. Chandler, AZ 85226,
[3]S.M.Sze”semiconductor sevice physics and Technology 2nd edition” wiley
[4]Marvin H. White, Yang (Larry) Yang,, Ansha Purwar, Margaret L”. A Low Voltage SONOS Nonvolatile Semiconductor Memory Technology” IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART A, VOL. 20, NO. 2, JUNE1997 ,p190
[5]Marvin H.White dennis .A Adams.jiankang Bu,”on the go with sonos”IEEE circuits and device july 2000
[6]Laurent Breuil, Luc Haspeslagh, Pieter Blomme, Dirk Wellekens, Joeri De Vos, Martino Lorenzini, andJan Van Houdt,” A New Scalable Self-Aligned Dual-Bit Split-Gate Charge-Trapping Memory Device”IEEE VOL. 52, NO. 10, OCTOBER 2005
[7]B. Eitan, P. Pavan, I. Bloom, E. Aloni, A. Frommer, and D. Finzi, “NROM: A novel localized trapping, 2-bit nonvolatile memory cell,” IEEE Electron Device Lett., vol. 21, pp. 543–545, Aug. 2000
[8]Kam Hung Yuen, Tsz Yin Man, Student Member, IEEE, Alain C. K. Chan” A2-Bit MONOS Nonvolatile Memory Cell Based on Asymmetric Double Gate MOSFET Structure” IEEE VOL. 24, NO. 8, AUGUST 2003
[9]P. Pavan, R. Bez, P. Olovo, and E. Zanoni, “Flash memory cells-an overview,”Proc. IEEE, vol. 85, pp. 1248–1271, Aug. 1997
[10]P. E. Cottrell, R. R. Troutman, and T. H. Ning, “Hot-electron emission in n-channel IGFET’s,” IEEE Trans. Electron Devices, vol. ED-26, no. 4, pp. 520–532, 1979.
[11]B. Eitan and D. Froham-Bentchkowsky, “Hot-electron injection into the oxide in n-channel MOS devices,” IEEE Trans. Electron Devices, vol. ED-28, no. 3, pp. 328–340, 1981.
[12]E. Takeda, H. Kune, T. Toyabe, and S. Asai, “Submicrometer MOSFET structure for minimizing hot-carrier generation,” IEEE Trans. Electron Devices, vol. ED-29,no. 4, pp. 611–618, 1982
[13]K. Hess and C. T. Sah, “Hot carriers in Silicon surface inversion layers,” J. Appl. Phys., vol. 45, p. 1254, 1974
[14]T.Ning.C.Osburn and H.YU.”Emission probability of hot electron from silicon into silcon dioxide,.J.April.physical.,vpl.48,1977,PP.286
[15]C.Hu,S.Tam,F.Hsu,P.Ko,T.Chan and K.Terrial.”Hot-Electron Induced MOSFET Degration-Model,Monitor and improvement,IEEE Trans.Electron device ED-32,1985 pp.375
[16]Boaz Eitan, Paolo Pavan, Iilan Bloom ,Efraim Aloni ,Aviv Frommer, David Ffinzi”can nrom 2bit trapping storage NVM cell,give a real chanllenge to floating gate cell?” present at international conference on solid device and material ,Tokyo 1999
[17]L. Esaki, “Long journey into tunneling,” Proc. IEEE, vol. 62, pp. 825–831, June 1974
[18]J. Moll, Physics of Semiconductors. New York: McGraw-Hill,1964
[19]M. Lezlinger and E. H. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,” J. Appl. Phys., vol. 40, no.1, pp.278–283, 1969
[20]T.Y.CHAN,K.K Yang HU,”A true single transistor oxide-nitride-oxide EEPROM”， IEEE electron device letters.EDL-8,vol3,march，1987,pp.93~95
[21]Cheng T. Wang. “ hot carrier design consideration for mos device and circuit” New York: Van Nostrand Reinhold, 1992, ch. 2
[22]W.S.Feng,T.Y.Chan and C.Hu “Mosfet drain breakdown voltage”.IEEE electron device lett., vol.EDl-6 july 1986, pp.449
[23]M.S. Liang and T.C.Lee,”a hot hole Eraseable Memorry Cell” IEEE electron device lett.,Vol,EDL-7,aug .1986, pp. 463
[24]Boaz Eitan”Two bit nonvolatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping” U.S.Patent 6,011,725, Oct.03,2006
[25].J.Tsai,N.K.Zous,C.K.Liu,C.C.Liu,C.H.Chan,Tahui Wang,San Pan and Chih-Yuan, Lu,”Data Retention Behavior of a SONOS Type Two Bit Storage Flash Memory Cell”,Electron Device Meeting,IEDM Technical Digest.International,2001,PP.32.6.1~32.6.4
[26]Yakov Roizin,Micha Gutman,efriam Aloni,Victor Kairys,pavel Zisman,”Retention Characteristic of microFlash Memory(Actionvation Energy of Trap in the ONO stack)”
[27].J.Tsai,N.K.Zous,C.K.Liu,C.C.Liu,C.H.Chan,Tahui Wang,San Pan and Chih-Yuan, Lu,”Cause of Data retention Loss in a Nitride-Based Localized Trapping Storage Flash Memory Cell”IEEE Annual International Reliability Physics Symposium,2002.pp.34~38
[28]James B. Kuo and Ker-Wei Su” CMOS VLSI engineering : silicon-on-insulator (SOI)” Kluwer Academic Publishers, 1998