臺灣博碩士論文加值系統

近年來，半導體產業以及國家政府安全國防機構開始研究以及關切硬體安全議題，其中一個主題是在積體電路(IC)中被插入惡意的邏輯閘，我們稱為硬體木馬。
由於硬體木馬本身是具有隱藏的性質，只有在罕見的情況下才會被觸發，這使得它很難被發現，傳統的偵測方法使用隨機向量去觸發木馬電路，在通常的情況下這種方法的效率並不高。
在此篇我們首先討論如何有效率的建構組合木馬。一開始先產生觸發訊號的候選集合，然後分析這些訊號之間的相關性，從而建立有效的觸發條件。由於考量到佈局的限制，許多觸發條件無效的，因此我們提出一種考量佈局條件的方法去建立木馬與產生觸發向量。
根據實驗結果可得知，藉由佈局條件的幫助下，觸發訊號會有明顯的下降。這項研究的結果應該有助於木馬偵測的發展。

In recent years, the semiconductor industry and the government agencies on national security and defense are starting to pay attention to hardware security issues, including the idea of inserting malicious logic gates into integrated circuit, which we call hardware Trojans.
Since hardware Trojans are stealthy in nature and triggered only under rare conditions, which make them hard to detect. Traditional Trojan activation methods rely on applying random patterns to trigger Trojan circuit; unfortunately, this approach is not efficient in general.
In this paper, we discuss how to construct combinational Trojans efficiently. A set of candidate trigger signals is obtained first, and then dependency among those signals is analyzed so that efficient trigger conditions can be constructed. Since many trigger conditions are not valid when layout constraints are taken into account, we propose a layout-aware approach for Trojan construction and activation vector generation.
According to the experimental results, the number of activation vectors is significantly reduced with the help of layout information. The results of this study should be helpful to the development of Trojan detection methods.

摘要 i
Abstract ii
目錄 iii
表目錄 iv
圖目錄 v
第一章 簡介 1
1.1. 研究動機與目標 1
1.2. 內容大綱 2
第二章 初步的介紹 4
2.1. 硬體木馬與偵測方法 4
2.2. 組合木馬的觸發條件 8
第三章 選擇觸發訊號 10
3.1. 觸發訊號候選集合 10
3.2. 觸發訊號的位置 11
3.3. 結構性相依 12
3.4. 邏輯性相依 17
第四章 硬體木馬的測試向量產生方法 22
4.1. 選擇並分類罕見事件 23
4.2. 建立基於佈局的聯合事件 24
第五章 實驗結果 29
5.1.統計等價與相依集合的個數 30
5.2.對於聯合事件測試向量產生結果 33
第六章 結論 36
參考文獻 37

[1]M. Tehranipoor and F. Koushanfar, “A survey of hardware Trojan taxonomy and detection,” IEEE Des. Test. Comput., vol. 27, pp. 10–25, 2010.
[2]R. Karri, J. Rajendran, K. Rosenfeld, and M. Tehranipoor, “Trustworthy hardware: Identifying and classifying hardware Trojans,” IEEE Comput., vol. 43, no. 10, pp. 39–46, 2010.
[3]J. Rajendran, E. Gavas, J. Jimenez, V. Padman, and R. Karri, “Towards a comprehensive and systematic classification of hardware Trojans,” in Proc. IEEE Int. Symp. Circuits and Syst. (ISCAS), pp. 1871–1874, 2010.
[4]R. Rad, J. Plusquellic, and M. Tehranipoor, “Sensitivity analysis to hardware Trojans using power supply transient signals,” in Proc. IEEE Int. Workshop on Hardware-Oriented Security and Trust, 2008, pp. 3–7.
[5]Y. Jin, N. Kupp, and Y. Makris, “Experiences in hardware Trojan design and implementation,” in Proc. IEEE Int. Workshop Hardware-Oriented Security and Trust, 2009, pp. 50 –57.
[6]G. Bloom, B. Narahari, and R. Simha, “OS support for detecting Trojan circuit attacks,” in Proc. IEEE Int. Workshop Hardware-Oriented Security and Trust. 2009, pp. 100–103.
[7]R.S. Chakraborty and S. Bhunia, “Security against hardware Trojan through a novel application of design obfuscation,” in Proc. Int. Conf. Comput.-Aided Des., 2009, pp. 113–116.
[8]H. Salmani, M. Tehranipoor, and J. Plusquellic, “A novel technique for improving hardware Trojan detection and reducing Trojan activation time,” IEEE Trans. Very Large Scale Integr. (VLS) Syst., vol. 20, no. 1, pp. 112–125, Jan. 2012.
[9]M. Banga and M.S. Hsiao, “A novel sustained vector technique for the detection of hardware Trojans,” in Proc. IEEE Int. Conf. VLSI Des., 2009, pp. 327–332.
[10] Y. Jin and Y. Makris, “Hardware Trojan detection using path delay fingerprint,” in Proc. IEEE Int Workshop on Hardware-Oriented Security and Trust, 2008, pp. 51–57.
[11] S. Deyati, B. Muldrey, A. Singh, and A. Chatterjee1, “High resolution pulse propagation driven Trojan detection in digital logic: optimization algorithms and infrastructure,” in Proc. IEEE Asian Test Symp., 2014, pp. 200–205.
[12] J.-F. Zheng, Static Compaction Algorithm for Clock Delay Faults, Master Dissertations of National Chung Hsing University C.S., July 2015
[13] T.-J. Chiu, A Novel side-channel Attack on Secured Scan Chain, Master Dissertations of National Chung Hsing University C.S., July 2015
[14] J.-Y. Wei, A Study on Hardware Trojans and Detection, Master Dissertations of National Chung Hsing University C.S., July 2015
[15] S.-J. Wang, J.-Y. Wei, S.-H. Huang, and K. S.-M. Li, “Test generation for combinational hardware Trojans,” in Proc. IEEE Asian Hardware-Oriented Security and Trust Symp. (AsianHOST), 2016