臺灣博碩士論文加值系統

本論文透過碩造無氧高矽的環境改變鍺間隙子在二氧化矽柱內的運動情形。藉由依序沉積0/9/25nm之非晶矽覆蓋層及9nm氮化矽覆蓋層，在包覆著鍺間隙子的二氧化矽柱外圍，並給予熱回火。高溫會促進非晶矽釋放矽間隙子，造成二氧化矽柱內的鍺間隙子會產生奧斯瓦德熟化反應，促使鍺間隙子團聚成結晶性良好的量子點，量子點大小範圍擴及10nm~70nm。與此同時部分鍺間隙子會析出至非晶矽覆蓋層，使之轉變成鍺濃度約15%的複晶矽鍺層。
此種方式形成的複晶矽鍺層，可以達到<10nm的厚度，且表面平整度極佳。對於電晶體通道而言，是絕佳的材料。故本論文嘗試把鍺擴散形成的複晶矽鍺層，應用在垂直通心粉電晶體的通道層上。並開發全新的製程去製作矽鍺通道之通心粉電晶體。新製程已成功製作出適用於垂直通心粉電晶體的矽鍺通道層、源極、閘極，並展現可以高密度製作通心粉電晶體的潛力，但在汲極製作上遇到困難，仍需進一步改善。

In this thesis, we create an low oxygen interstitials, but high silicon interstitials environment to affect Ge interstitials which are inside SiO2 pillar. Lithographically-patterned SiGe nanopillars were subsequently oxidized at 900oC in an H2O ambient in which the Si content is preferentially oxidized and Ge nanorystallite clusters are produced and embedded within the resulting SiO2 matrix. Subsequently, the oxidized pillars were encapsulated with a conformal deposition of “capping layers” of Si3N4 and/or amorphous Si (a-Si). After encapsulation, the oxidized pillars were further subjected to thermal anneal at 900oC in an H2O ambient. The released Si interstitials were found to significantly facilitate the growth and migration of the Ge interstitials generated from the selective oxidation of the poly-SiGe nanopillars. By this chemical mechanism, we can fabricate Ge QDs (diameter from 10nm ~70nm) and ultra thin (<10nm) SiGe layer which is very useful as transistor’s channel material. We try to apply this SiGe layer on macaroni transistors and design a new vertical SiGe macaroni transistors fabrication process. Also, demonstrate the structure of SiGe channel, source, gate of vertical SiGe macaroni transistors.

中文摘要 i
英文摘要 ii
致謝. iii
目錄 ………………………………………………………………………………….v
圖次. vii
第一章、實驗動機與簡介 1
1-1非揮發記憶體現況簡介 1
1-2 3D NAND記憶體介紹 2
1-2-1傳統2D記憶體進行3D堆疊 2
1-2-2 Bit Cost Scalable (BiCS) device介紹 3
1-3研究動機 & 論文架構 4
1-3-1 研究動機 4
1-3-2論文架構 5
第二章、 藉由Si、Ge及O三者交互作用來控制鍺間隙子在二氧化矽柱中的運動情形 10
前言 10
2-1實驗設計 10
2-2實驗方法&目的 11
2-3 實驗製作流程 12
2-4 實驗結果與討論 12
2-4-1 TEM照片觀察 12
2-4-2 量子點形成分析與討論 13
2-4-3 非晶矽轉變成矽鍺分析與討論 15
2-4 結論 18
第三章、垂直通心粉電晶體製程開發與電性分析 25
前言 25
3-1 垂直通心粉電晶體製程設計 25
3-2 元件製作流程與結果討論 28
3-3 電性分析與討論 32
3-4 製程開發結論與改善方式 32
第四章、未來展望 50
參考文獻 51
Vita ………………………………………………………………………………...54

1. S.-M. Jung, J. Jang, W. Cho, H. Cho, J. Jeong, Y. Chang, J. Kim, Y. Rah, Y. Son, J. Park, M.-S. Song, K.-H. Kim, J.-S. Lim, and K. Kim, “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node,” 2006 International Electron Devices Meeting, 2006.
2. E.-K. Lai, H.-T. Lue, Y.-H. Hsiao, J.-Y. Hsieh, C.-P. Lu, S.-Y. Wang, L.-W. Yang, T. Yang, K.-C. Chen, J. Gong, K.-Y. Hsieh, R. Liu, and C.-Y. Lu, “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” 2006 International Electron Devices Meeting, 2006.
3. Y. Fukuzumi, R. Katsumata, M. Kito, M. Kido, M. Sato, H. Tanaka, Y. Nagata, Y. Matsuoka, Y. Iwata, H. Aochi, and A. Nitayama, “Optimal Integration and Characteristics of Vertical Array Devices for Ultra-High Density, Bit-Cost Scalable Flash Memory,” 2007 IEEE International Electron Devices Meeting, 2007.
4. J. V. Houdt, “Memory technology for the terabit era: From 2D to 3D,” 2017 Symposium on VLSI Technology, 2017.K. H. Chen, C. C. Wang, T. George, and P. W. Li, “The pivotal role of SiO formation in the migration and Ostwald ripening of Ge quantum dots,” Applied Physics Letters, vol. 105, no. 12, p. 122102, 2014.
5. C.-C. Wang, P.-H. Liao, M.-H. Kuo, T. George, and P.-W. Li, “The curious case of exploding quantum dots: anomalous migration and growth behaviors of Ge under Si oxidation,” Nanoscale Research Letters, vol. 8, no. 1, p. 192, 2013.
6. G. Hadjisavvas, I. N. Remediakis, and P. C. Kelires, “Shape and faceting of Si nanocrystals embedded ina−SiO2: A Monte Carlo study,” Physical Review B, vol. 74, no. 16, 2006.Bb
7. A. A. Stekolnikov and F. Bechstedt, “Shape of free and constrained group-IV crystallites: Influence of surface energies,” Physical Review B, vol. 72, no. 12, 2005.
8. V. E. Gusakov, “General Model of Diffusion of Interstitial Oxygen in Silicon, Germanium and Silicon - Germanium Crystals,” Solid State Phenomena Gettering and Defect Engineering in Semiconductor Technology XI, pp. 413–418, 2005.
9. V. I. Kalikmanov, Nucleation theory. Dordrecht: Springer, 2013.
10. S. Kumar, Raman spectroscopy. Atlanta: School of Textile and Fiber Engineering, Georgia Institute of Technology, 2003.
11. R. Liu, B. Tillack, and P. Zaumseil, “Raman Characterization of Composition and Strain in Si1−xGex/Si Heterostructures,” MRS Proceedings, vol. 591, 1999.
12. Parker, J. H., Feldman, D. W., & Ashkin, M. (1967). Raman Scattering by Silicon and Germanium. Phys. Rev. Physical Review, 155(3), 712-714. doi:10.1103/physrev.155.712
13. Burke, H. H., & Herman, I. P. (1993). Temperature dependence of Raman scattering in Ge 1 − x Si x alloys. Phys. Rev. B Physical Review B, 48(20), 15016-15024. doi:10.1103/physrevb.48.15016
14. F. Pezzoli, E. Bonera, E. Grilli, M. Guzzi, S. Sanguinetti, D. Chrastina, G. Isella, H. V. Känel, E. Wintersberger, J. Stangl, and G. Bauer, “Raman spectroscopy determination of composition and strain in heterostructures,” Materials Science in Semiconductor Processing, vol. 11, no. 5-6, pp. 279–284, 2008.
15. B.-H. Lee, M.-H. Kang, D.-C. Ahn, J.-Y. Park, T. Bang, S.-B. Jeon, J. Hur, D. Lee, and Y.-K. Choi, “Vertically Integrated Multiple Nanowire Field Effect Transistor,” Nano Letters, vol. 15, no. 12, pp. 8056–8061, Nov. 2015.
16. R. Gandhi, Z. Chen, N. Singh, K. Banerjee, and S. Lee, “Vertical Si-Nanowire n-Type Tunneling FETs With Low Subthreshold Swing (≤50mV/deceade ) at Room Temperature,” IEEE Electron Device Letters, vol. 32, no. 4, pp. 437–439, 2011.