臺灣博碩士論文加值系統

本篇論文中，吾人提出並證實一種只利用一道光罩即能形成氧化鋅通道與源極/汲極電極的方法，可明顯簡化氧化鋅薄膜電晶體的製作流程。除了上述的新觀念外，光阻削薄技術也被應用以有效縮短氧化鋅薄膜電晶體的閘極長度。透過此技術，次100奈米的氧化鋅薄膜電晶體被成功的製作出來，其電子遷移率約為1.11 cm2V-1s-1，開關比達107，次臨界擺幅207 mV/decade。此元件能夠做為研究奈米級氧化鋅薄膜電晶體的先驅。
另外，不同閘極長度和通道厚度的氧化鋅薄膜電晶體也被分析與比較。對於短通道的氧化鋅薄膜電晶體而言，源極/汲極的寄生串連電阻顯著地影響著元件的輸出特性。因此，在輸出曲線中幾乎呈線性表現，無明顯的飽和區段。而串連電阻的主要來源應是源極/汲極電極與氧化鋅通道間有一層非晶態的薄膜。而這層非晶態的薄膜可以經由X射線光電子能譜分析後證實為氧化鋁。

In this thesis, a new concept to form ZnO channel layer and source/drain electrodes in the fabrication of ZnO TFTs using only one mask is proposed and demonstrated. The modified process can greatly simplify the fabrication process of ZnO TFTs. In addition to revealing the above concept, the photoresist (PR) trimming technique is employed to shrink the channel length of ZnO TFTs. Through taking advantage of the technique, sub-100 nm ZnO TFT is successfully fabricated. The device shows field-effect mobility of 1.11 cm2V-1s-1, on/off current ratio of 107, and S.S. of 207 mV/decade. The structure developed in this thesis can serve as a test vehicle for studying the nano-scale ZnO TFT devices.
Besides, ZnO TFTs with different channel length and channel thickness are also investigated. For short-channel ZnO TFTs, the parasitic source/drain resistance dominates the total resistance and the output characteristics shows hard saturation and output drain current becomes almost linear with drain voltage. The origin of the high parasitic source/drain resistance is that there exists an amorphous layer between ZnO channel and Al source/drain pads. From the XPS analysis, the amorphous layer is identified to be Al2O3.

Abstract (Chinese)……………………………………………………..ⅰ
Abstract (English)……………………………………………………...ⅱ
Acknowledgement……………………………………………………...ⅳ
Contents………………………………………………………………...ⅴ
Table Captions…………………………………………………………ⅷ
Figure Captions……………………………………………………...…ⅸ

Chapter 1 Introduction…………………………………………………1
1.1 Metal Oxide Thin-Film Transistors (TFTs)………………………………….1
1.2 Properties of ZnO…………………………………………………………….. 3
1.3 The Structure of TFTs…………………………………………………………5
1.4 Motivation and Objectives…………………………………………………….6
1.5 Organization of this Thesis…………………………………………………..7

Chapter 2 Device Fabrication and Measurement Setup……………...8
2.1 Process Flow of ZnO Thin-Film Transistors with Engineered Deposited Film Profile…………………………………………………………………………...8
2.2 Effects of Deposition Pressure…………………………………………………9
2.3 Parameter Extraction…………………………………………………………10
2.4 The Measurement Setup……………………………………………………...12

Chapter 3 Results and Discussion…………………………………….13
3.1 Photoresist Trimming………………………………………………………...13
3.2 Fundamental Electrical Characteristics of A Sub-0.1um TFT……………..14
3.3 The ZnO TFTs with Different Length of Hard Mask………………………18
3.4 Effects of Al Deposition……………………………………………………….20
3.5 Comparison with Benchmark Data from the Literature for Sub-100 nm Metal Oxide TFTs…………………………………22

Chapter 4 Conclusion and Future Work……………………………..24
4.1 Conclusion……………………………………………………………………..24
4.2 Future Work…………………………………………………………………...25

References………………………………………………………………………27
Tables……………………………………………………………………………36
Figures…………………………………………………………………………39
Vita………………………………………………………………………………64

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