臺灣博碩士論文加值系統

基於無線千兆聯盟(WiGig)所提出的高速無線網路60 GHz Wifi 標準( IEEE 802.11ad )，為了將傳輸速率提升至10Gbps，本論文修改802.11ad中的頻譜遮罩，重新定義每個頻道的中心頻率，並且提升所需的相位雜訊要求，然而，在寬操作頻率(47.5~52.5 GHz)及低相位雜訊( <-93dBc/Hz @1MHz)的要求下，對高頻之頻率合成器更不易設計。本論文提出一頻率合成器，其操作電壓為1V，採用互補式交叉耦合諧振電壓控制振盪器(LC VCO)，可降低相位雜訊的輸出；前兩級之迴路除頻器選用電流模式邏輯除頻器(CML Divider)，有足夠的操作範圍及減小面積等優點；此論文於台積28奈米半導體製程下實現，在不同的輸出頻率下，頻率合成器消耗的總功率都在22 mW以下，相位雜訊方面，呈現的結果為 -102 dBc/Hz @1 MHz以下，為低功耗、低相位雜訊的頻率合成器。

In order to increase data rate of IEEE 802.11ad proposed by WiGig to 10Gbps, this paper modifies spectrum mask, redefines center frequency of each channel, and increases phase noise constrain. However, under wide range of operating frequency (47.5~52.5 GHz) and low phase noise (-93dBc/Hz@1MHz) requirements, such high frequency synthesizer is more difficult for circuit design. This paper proposes a frequency synthesizer that operates at 1V. It adopts complementary cross couple LC voltage control oscillator which can lower phase noise of output and uses CML divider which can provide enough operation range and lower consumption of area. This work implements in 28 nm CMOS technology. The simulation of synthesizer shows that the average power consumption is below 22 mW at operating range, and the phase noise at output is around -102dBc/Hz @1MHz.

第一章 緒論 1
1-1研究動機與背景介紹 1
1-2論文架構 4
第二章 收發機的介紹及規格訂定 6
2-1發射機架構介紹 6
2-2接收機架構介紹 7
2-3射頻無線系統收發機 7
2-4相位雜訊對通訊系統的影響 13
2-5頻道規劃、參考頻率的制定 15
第三章 鎖相式頻率合成器 21
3-1 頻率合成器簡介 21
3-2 鎖相迴路轉移函數分析 24
3-3 鎖相迴路雜訊分析 27
3-3.1雜訊的種類 28
3-3.2鎖相迴路中各子電路的雜訊分析 31
3-3.3電壓控制振盪器相位雜訊分析 32
3-4 文獻回顧 37
第四章 無線傳輸系統之毫米波頻率合成器 42
4-1 頻率合成器架構介紹 42
4-2 相位頻率偵測器(PFD) 43
4-3電流泵(CP) 45
4-4壓控振盪器(VCO) 46
4-4.1振盪器架構分析 46
4-4.2高寬頻壓控振盪器之設計 49
4-5頻率除頻器(Divider) 57
4-5.1電流模式邏輯除頻器(CML Divider) 58
4-5.2 程式化除頻器(Programmable Divider) 60
4-6迴路濾波器設計 60
第五章 系統模擬 63
5-1閉迴路特性模擬 63
5-1.1 Simulink行為模擬 63
5-1.2 頻率合成器系統模擬 67
5-1.3 模擬討論 71
5-2 頻率合成器相位雜訊模擬 72
5-4 效能比較 74
第六章 結論 76
第七章 參考文獻 77

[1] Rowson, ” Wifi新標準到來：提速4倍，下載一部藍光電影只要46秒,” available online : http://tech2ipo.com/10034090
[2] A.Boveda, F.Orgitoso, and J.I.Alonso, ”A 0.7-3GHz QPSK/QAM direct modulator,” IEEE Journal Solid-State Circuits, vol.28, no.12, pp.1340-1349, Dec.1993.
[3] Glover, I. and Grant, P., Digital Communications. Pearson Education Ltd., 2004.
[4] Hua-Yu Liao, “Weaver-Hartley Image Rejection Down Converter and Dual Band Low Noise Amplifier,” MS thesis, Institute of Communications Engineering, National Chiao Tung University, 2006.
[5] B. Razavi, Design of analog CMOS integrated circuits, New York：McGraw-Hill, 2001. F
[6] T.C. Lee and B. Razavi, "A stabilization technique for phase-pocked frequency synthesizers," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 888-894 , Jun. 2003.
[7] A. Madisetti, A. Y. Kwentus, and A. N. Willson, “A 100-MHz,16-b, Direct Digital Frequency Synthesizer with a 100-dBc Spurious-Free Dynamic Range,” IEEE Journal Solid-State Circuits, vol. 34, no.8, August 1999.
[8] 劉深淵, 楊清淵, 鎖相迴路, 滄海書局, 2006
[9] B. Razavi, “A Study of Phase Noise in CMOS Oscillators," IEEE J. Solid-StateCircuits, vol. 31, no. 3, pp. 331-343, Mar. 1996.
[10] C.H. Lee, K. McClellan, and J. Choma, “A supply noise insensitive PLL design through PWL behavioral modeling and simulation," IEEE Trans. Circuits Syst. II,Analog Digit. Signal Process, vol. 48, no. 12, pp. 1137-1144, Dec. 2001.
[11] X. Gao, E. A. M. Klumperink, P. F. J. Geraedts, and B. Nauta, "Jitter analysis and a benchmarking figure-of-merit for phase-locked loops", IEEE Trans. Circuits Syst. II Reg. Papers, vol. 56, no.2, pp. 117-121, Feb. 2009
[12] E.Hegazi, H. Sjoland and A. A. Abidi, “A filtering technique to lower oscillator phase noise,” IEEE J. Solid-State Circuits, vol.36,No.12, pp.1921-1930, Dec.2001.
[13] J. J. Rael and A. A. Abidi, “Physical processes of phase noise in differential LC oscillators,” in Proc. IEEE Custom Integrated Circuits Conf., Orlando, FL, 2000, pp.569-572
[14] D. Li, L. Zhang, and Y. Wang, “A 60GHz quadrature LO synthesizer with 1.2° phase error and over 17% tuning range for IEEE 802.11ad applications,” in Proc. IEEE ICSICT, pp. 1-3, Oct. 2014
[15] V. Szortyka et al., “A 42 mW 230 fs-jitter sub-sampling 60 GHz PLL in 40 nm CMOS,” in proc. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 366–367 , Feb. 2014.
[16] Y. Chao and H. C. Luong, “Analysis and design of a 2.9-m 53.4–79.4-GHz frequency-tracking injection-locked frequency divider in 65-nm MOS,” IEEE J. Solid-State Circuits, vol. 48, no. 3, pp.652–660, Oct. 2013.
[17] Y.-H. Wong, W.-H. Lin, J.-H. Tsai, and T.-W. Huang, “A 50-to-62 GHz wide - locking-range CMOS injection-locked frequency divider with transformer feedback,” in Proc. Radio Freq. Integr. Circuits Symp. , pp. 435–438, Jun.17.2008.
[18] W. Nam, J. Son and H. Shin, "Design of a 40GHz PLL Frequency Synthesizer with Wide Locking Range ILFD in 65nm CMOS," in Proc. International SoC Design Conf. (ISOCC), pp. 23-24 31, Nov. 2015.
[19] B. Sadhu, M. Ferriss, and A. Valdes-Garcia, “A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance,” IEEE J. Solid-State Circuits, vol.50, no.5, pp.1214-1223 ,May. 2015.
[20] D. Murphy et al., “A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15.3c transceiver,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1606–1617, Jul. 2011.
[21] J. Luo; L. Zhang, L. Zhang, Y. Wang, and Z. Yu, "A 24GHz low power and low phase noise PLL frequency synthesizer with constant KVCO for 60GHz wireless applications," in Proc. IEEE International Symp. on Circuits and Syst., pp.2840-2543, 24-27 ,May 2015.
[22] Zhou B, Zhang L, Wang Y, Yu Z., “A 56-to-66 GHz quadrature phase-locked loop with a wide locking range divider chain in 65 nm CMOS,” in Proc. of IEEE International Conf. on Electron Devices and Solid-State Circuits (EDSSC), Singapore, 455–458, 1-4 January 2015.
[23] A. Li, S. Zheng, J. Yin, X. Luo, H. C. Luong, "A 21–48 GHz subharmonic injection-locked fractional-N frequency synthesizer for multiband point-to-point backhaul communications", IEEE J. Solid-State Circuits, vol. 49, no. 8, pp. 1785-1799 , Aug. 2014.
[24] O. Richard, A. Siligaris, F. Badets, C. Dehos, C. Dufis, P. Busson, P. Vincent, D. Belot, and P. Urard, “A 17.5-to-20.94 GHz and 35-to-41.88 GHz PLL in 65 nm CMOS for wireless HD applications,” in Pro. IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp.252–253, Feb. 2010.
[25] Z. Zong, M. Babaie, and R. B. Staszewski, “A 60 GHz frequency generator based on a 20 GHz oscillator and an implicit multiplier,” IEEE J. Solid-State Circuits, vol. 51, no. 5, pp. 1261–1273, May 2016.
[26] J. S. Lee et al., “Charge pump with perfect current matching characteristics in phase-locked loops,” Electron. Lett., vol. 36, no. 23, pp. 1907–1908, Nov. 2000.
[27] B. Razavi, RF Microtronics, Prentice Hall PTR, 1998.
[28] Yannis P. Tsividis, Operation and Modeling of the MOS Transistor, McGraw-Hill International Edition, Ch. 2, 1987
[29] Thomas H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, 2nd edition, Cambridge, 2004.
[30] Ali Hajimiri, Thomas H. Lee, The Design of Low Noise Oscillators, Kluwer Academic Publishers, 1999.
[31] T. Siriburanon et al., "A 60-GHz sub-sampling frequency synthesizer using sub-harmonic injection-locked quadrature oscillators", in proc. IEEE Radio Frequency Integrated Circuits Symp. (RFIC) Dig., pp. 105-108 , Jun. 2014.
[32] A. Kral, F. Behbahani, A. A. Abidi, "RF-CMOS oscillators with switched tuning", in Proc. IEEE Custom Integrated Circuits Conf., pp. 555-558, 1998.
[33] H. Sjland, "Improved switched tuning of differential CMOS VCOs", IEEE Trans. Circuits Syst. II Analog Digit. Signal Process., vol. 49, no. 5, pp. 352-355, May 2002.
[34] M. Usama, T. A. Kwasniewski, "A 40-GHz Frequency Divider in 90-nm CMOS Technology," in Proc. IEEE North-East Workshop on Circuits and Syst., pp. 41-43, 2006.
[35] E. Hegazi, J. Rael ,and A. Abidi. The Designer's Guide to High-Purity Oscillators. Springer, 2004.