臺灣博碩士論文加值系統

本論文旨在設計V頻段的無線通訊系統射頻前端電路。針對採用超外差架構之收發機，本論文完成超外差式升頻混波器的設計，另外也完成接收機前端之整合電路。本論文內容於所設計的電路，均包含電路原理簡單的介紹、電路設計、模擬以及晶片量測結果。以下為本論文內容之概要：
第一部分首先針對無線通訊系統架構的應用作介紹，以及常見收發機架構的簡介，並回顧相關文獻。
第二部分為收發機架構與混波器的種類與原理的介紹。
第三部分的內容為整合應用於V頻段的超外差式升頻混波器的電路設計，包含由第一級基頻升至12GHz中頻的混波器，以及完整的外差升頻至60GHz的電路。其中第一級主要採用吉伯特結構設計去變化，在轉導級採用線性化改善技巧，並於輸出級改採電阻回授反相器作為輸出緩衝器。第二級升頻混波器則為採用開關式被動混波器的電路設計，來改善線性度不足的問題，由上述兩級的混波器整合成超外差式升頻混波器。
第四部分則為外差式接收機整合電路設計，利用先前本實驗室的學長們下線驗證過的電路，分別為應用在60GHz的低雜訊放大器與外差式降頻混波器，以及一些被動元件設計，包含相位轉移器、平衡轉不平衡轉換器、中央抽頭電感等被動元件設計。並將這些電路整合成一完整之接收機電路完成下線。

The purpose of this thesis is to present the integration design of the RF front end for a V-band wireless communication system. Based on the superheterodyne architecture, this thesis proposed the up-conversion mixer architecture and a complete receiver front end. Each circuit proposed in this thesis includes its design principle, circuit design, simulated results, and chip measurement results, as well as a brief discussion. The content of this thesis is as following:
The first part introduces the systematic structure of wireless communication applications, as well as the introduction of the transceiver architectures with a short survey on previous researches.
The second part is an introdution of classification and the principle of transceiver architectures and mixers.
The content of the third part is the V-band superheterodyne up conversion mixer circuit design which includes a baseband to 12GHz IF first stage and a 12GHz-to-60GHz stage. The first stage of up-conversion mixer circuit is based on the Gilbert cell with a linearity-improved trans-conductance stage and a resistive-feedback inverter as its output buffer. And the second stage of up conversion mixer adopts the switching passive mixer circuit design which can improve the linearity problem. The integration of the described two kind of mixers forms a complete superheterodyne up conversion mixer.
The fourth part is the integration of a heterodyne receiver circuit design for the 60GHz applications, which includes some of verified circuits proposed by prvious seniors of our laboratory, including the low noise amplifier (LNA), heterodyne down-conversion mixers, and some passive components designs such as the polyphase filter, marchand Balun, center-tapped inductive passive components. We integrate these sub-circuit into a complete receiver front end and successfully tape-out.
We make a simple conclusion and short discussion of the possible study for the future research and work in the last part.

致謝 I
摘要 III
Abstract IV
目錄 VI
圖目錄 VIII
表目錄 XI
第一章 緒論 1
1.1 無線通訊系統的介紹 1
1.2 毫米波介紹與60GHz應用 7
1.3 文獻回顧 10
1.4 論文大綱 11
第二章 混波器的原理介紹 13
2.1 前言 13
2.2 混頻器架構介紹 13
2.2.1 架構簡介 13
2.2.2 基本架構介紹 15
2.2.3 開關式被動混波器(Switch type passive mixer) 16
2.2.4 電阻性混頻器(Resistive mixer) 16
2.2.5 單平衡式混波器(Single-balanced mixer) 18
2.2.6 雙平衡式主動混波器(Double-balanced mixer) 21
2.3 混頻器特性參數 25
2.3.1 輸入及輸出的匹配(Input and Output matching) 25
2.3.2 轉換增益(Conversion Cain) 26
2.3.3 線性度(Linearity) 27
2.3.3.1 1dB增益壓縮點(1-dB Gain Compressed Point,P1dB) 28
2.3.3.2 三階截距點(Third order intercept point,IP3) 30
2.3.4 雜訊指數(Noise Figure，NF) 33
2.3.5 隔離度(Isolation) 35
第三章 V-band之外差式升頻混頻器 38
3.1 混頻器電路原理與架構 38
3.1.1 電路原理 38
3.1.2 平衡與不平衡轉換器(Balun)的原理與種類介紹 41
3.1.2.1 耦合線被動式Balun 42
3.1.2.2 疊層螺旋形結構 43
3.1.2.3 疊層折線型結構 45
3.1.3 電阻回授反相器(resistive-feedback inverter) 47
3.1.4 轉導級 transconductance stage 49
3.1.4.1 電路介紹 49
3.1.4.2 暫態模擬圖 51
3.2 應用於超外差式之60GHz混頻器電路分析與設計 53
3.2.1 系統架構 53
3.2.2 基頻升至12GHz頻帶混頻器設計 54
3.2.2.1 電路架構 54
3.2.2.2 晶片攝影圖 55
3.2.2.3 基頻升至12GHz頻帶混頻器的模擬及量測結果 57
3.2.2.4 基頻升至12GHz頻帶混頻器的電路結果與討論 63
3.2.3 12GHz升至60GHz的第二次升頻混頻器設計 64
3.2.3.1 電路簡介 64
3.2.3.2 電路架構 64
3.2.4 基頻升至60GHz的二次升頻混頻器設計 66
3.2.4.1 電路簡介 66
3.2.4.2 電路佈局圖 67
3.2.4.3 操作於60GHz的二次升頻混頻器的模擬及量測結果 68
3.2.4.4 操作於60GHz的二次升頻混頻器的電路結果與討論 77
第四章 V-band外差式降頻接收機 78
4.1 接收機電路原理與架構 78
4.1.1 前言 78
4.1.2 接收機電路架構介紹 79
4.1.2.1 耦合結構與LNA設計介紹 81
4.1.2.2 60 GHz LNA的電路分析 83
4.1.3 60GHz降至12GHz頻帶混頻器電路分析 84
4.1.4 12GHz(中頻)降至基頻(Baseband)混頻器電路分析 88
4.1.5 Balun元件設計 90
4.1.6 polyphase filter結構介紹與電路設計 92
4.1.6.1 RC相位產生器(polyphase filter) 92
4.1.6.2 RC相位產生器的電路介紹 93
4.2 晶片模擬圖 94
4.3 接收機模擬結果 95
4.2.1 被動元件的模擬結果 95
4.2.2 Receiver的模擬結果 98
第五章 結論與未來展望 103
參考文獻 105

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