跳到主要內容

臺灣博碩士論文加值系統

(216.73.216.208) 您好!臺灣時間:2025/10/02 14:56
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

: 
twitterline
研究生:許睿軒
研究生(外文):Syu, Ruei-Syuan
論文名稱:應用於植入式醫療元件腦皮層電圖與電誘發複合活動電位紀錄之互補式金氧半類比前端生理訊號截取電路設計
論文名稱(外文):The Design of CMOS Analog Front-End Acquisition Circuits for Electrocorticography (ECoG) and Evoked Compound Action Potential (ECAP) Recording in Implantable Medical Devices
指導教授:吳重雨
指導教授(外文):Wu, Chung-Yu
口試委員:柯明道
口試委員(外文):Ker, Ming-Dou
口試日期:2019-06-13
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2019
畢業學年度:107
語文別:英文
論文頁數:136
中文關鍵詞:生理訊號擷取電路
外文關鍵詞:Analog Front-End Acquisition Circuits
相關次數:
  • 被引用被引用:0
  • 點閱點閱:276
  • 評分評分:
  • 下載下載:7
  • 收藏至我的研究室書目清單書目收藏:1
由於積體電路科技的發展及醫學的進步,使微小的電子醫療元件得以實現,用於神經生理訊號檢測系統,而可攜式或植入式裝置達到隨時隨地的健康檢測。在生理訊號的檢測系統中,類比前端電路十分重要,它必須要能有效地蒐集並放大生理訊號,並防止雜訊干擾,才能讓整體電路擁有良好的效能表現。
本論文主要針對兩種生理訊號,顱內腦波訊號(ECoG)及電誘發複合活動電位(ECAP),分別來設計類比前端電路。前者訊號的頻率約在0.5 Hz到100 Hz,振幅大約在0.1 mV到1 mV之間,所以設計的類比前端電路頻寬介於0.5 ~100Hz,具有三段可調的放大增益60.4/70.3/79.3 dB,輸入參考雜訊為0.95 μVrms,雜訊效率因子(NEF)為3.31。類比前端電路具有十六個通道,。此類比前端放大器包含了低雜訊前端放大器、可程式增益放大器、八通道多功器和轉阻放大器,功率消耗為95.2μW,平均每個通道所消耗的功率為5.95μW。後者訊號的頻率約在0.5 Hz到1K Hz,振幅大約在0.1 mV到2 mV之間,而設計的類比前端電路低頻截止頻率小於0.5 Hz、高頻截止頻率具有三段可調在150/606/1.25K Hz,並具有三段可調的放大增益59.8/69.8/79.8 dB,量測頻寬內的輸入參考雜訊為0.85 μVrms,功率消耗為9.0 μW,雜訊效率因子(NEF)約為2.31,為了使電路達到更低的雜訊,此電路使用了截波調變技術來移除電路本身在頻寬內的雜訊,並有三個回授電路,用以消除不理想效應。此類比前端電路由台灣積體電路製造股份有限公司製造以0.18微米製程實現。
This paper presents a 16-channel analog front-end (AFE) acquisition circuit for ECoG recording systems and a one channel analog front-end (AFE) acquisition circuit for ECAP recording systems. The former one consists of a 16 channel analog front-end amplifier (AFE Amplifier). The AFE Amplifier consists 16 analog front-end blocks, a 16-to-1 multiplexer, a trans-impedance amplifier (TIA). The latter one consists a chopper modulation low-noise preamplifier and Switched-Capacitor low-pass filter(SC-filter) and Switched-Capacitor amplifier (SC-Amp). They are designed for amplification and filtering the biopotential signals, these biopotential signals have the characteristics of small amplitudes, low frequency.
The AFE acquisition circuits which is fabricated in TSMC 0.18μm CMOS process can adjust gain at three steps (60.4/70.3/79.3dB) and (59.25/69.28/79.3dB) digitally, the high-pass corner can achieve as low as 0.5Hz and low-pass corner of former one can achieve 113 Hz, low-pass corner of latter one can adjust gain at three steps (150/606/1.25K) digitally. The input-referred noise is 0.95μVrms and 0.85μVrms. The noise efficiency factor is 3.31 and 2.31 of low-noise preamplifiers. The whole AFE acquisition circuit power consumption of former one is 95.2μW where 5.95μW per channel. The latter one is 73.4μW per channel.
摘要 I
Abstract II
Acknowledgements IV
Contents V
Figure Captions VII
Table Captions XIII
Chapter 1 Introduction 1
1.1 Background 1
1.2 Review on Analog Front-End 6
1.2.1 Review on ECoG AFE Amplifier without choppers 9
1.2.2 Review on ECAP AFE Amplifier 13
1.3 Motivation 15
1.4 Main Results and Thesis Organization 18
Chapter 2 Design of an Analog Front-End ECoG Acquisition Circuit 21
2.1 Design Consideration 23
2.1.1 Circuit Design Consideration 25
2.2 Analog Front-End Circuit Design 26
2.2.1 Low-Noise Pre-amplifier 28
2.2.2 Programmable Transconductance Gain Amplifier(PTGA) and Multiplexer 41
2.2.3 Trans-impedance Amplifier(TIA) 43
2.3 Post-Layout Simulation Results of AFE 47
Chapter 3 Design of an Chopper-Stabilized Analog Front-End ECAP Acquisition Circuit 52
3.1 Design Consideration 53
3.2 Chopper-Stabilized Analog Front-End Circuit Design 55
3.2.1 Inverter-Based Folded-Cascode Amplifier 58
3.2.2 Hybrid DC Servo Loop 60
3.2.3 Ripple Reduction Loop and Positive Feedback Loop 68
3.2.4 Stability Analysis of CCCIA 71
3.2.5 Switched-Capacitor 1st Order Low Pass Filter and Switched-Capacitor Amplifier 74
3.3 Post-Layout Simulation Results of Chopper-Stabilized AFE Amplifier 78
Chapter 4 Experimental Results 86
4.1 Chip Layout Descriptions 86
4.2 Measurement Setup 87
4.2.1 ECoG AFE Amplifier Measurement Setup 87
4.2.2 ECAP AFE Amplifier Measurement Setup 95
4.3 Measurement Results 101
4.3.1 ECoG AFE Amplifier Measurement Results 101
4.3.2 ECAP AFE Amplifier Measurement Results 107
4.4 Discussion of AFE acquisition circuit 115
4.4.1 Discussion of ECoG AFE Amplifier 115
4.4.2 Discussion of ECAP AFE Amplifier 118
4.4.3 Redesign of ECAP AFE Amplifier 120
Chapter 5 Conclusion and Future Work 127
5.1 Conclusion 127
5.2 Future Work 129
References 131
[1] M. A. Lebedev and M. A. Nicolelis, “Brain-machine interfaces: Past, present and future,” Trends Neurosci., vol. 29, no. 9, pp 36–546, Sep.2006.
[2] J. G. Webster, Medical instrumentation: application and design, Boston, Mass., USA: Houghton Mifflin, 2010.
[3] A. Rothermel, L. Liu, N. P. Aryan, M. Fischer, J. Wuenschmann, S. Kibbel, and A. Harscher, “A CMOS chip with active pixel array and specific test features for subretinal implantation,” IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 290–300, Jan. 2009.
[4] W.-M. Chen, et al., “A fully integrated 8-channel closed-loop neural-prosthetic CMOS SoC for real-time epileptic seizure control,” IEEE J. Solid-State Circuits, vol. 49, no. 1, pp. 232–247, Jan. 2014.
[5] C.-H. Cheng, et al., “A fully integrated closed-loop neuromodulation SoC with wireless power and bidirectional data telemetry for real-time human epileptic seizure control,” in Proc. Symp. VLSI Circuits. Dig. Tech. Papers, 2017, pp. C44–C45.
[6] P. T. Bhatti and K. D. Wise, “A 32-site 4-channel high-density electrode array for a cochlear prosthesis,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2965–2973, Dec. 2006.
[7] F.-G. Zeng, S. Rebscher, W. Harrison, X. Sun, and H. Feng, “Cochlear implants: system design, integration, and evaluation,” IEEE Rev. Biomed. Eng., vol. 1, pp. 115–142, Dec. 2008.

[8] F.-G. Zeng, S. J. Rebscher, Q.-J. Fu, H. Chen, X. Sun, L. Yin, L. Ping, H. Feng, S. Yang, S. Gong, B. Yang, H.-Y. Kang, N. Gao, and F. Chi, “Development and evaluation of the Nurotron 26-electrode cochlear implant system,” Hear. Res., vol. 322, pp. 188-199, Apr. 2015.
[9] X.-H. Qian et al., “A bone-guided cochlear implant CMOS microsystem preserving acoustic hearing,” in Proc. Symp. VLSI Circuits. Dig. Tech. Papers, June 2017, pp. C46–C47.
[10] P. E. Mohr, J. J. Feldman, and J. L. Dunbar, “The societal costs of severe to profound hearing loss in the United States,” Policy Anal. Brief H. Ser., vol. 2, no. 1, pp. 1–4, Apr. 2000.
[11] Abbas PJ, Brown CJ. Assessment of responses to cochlear implant stimulation at different levels of the auditory pathway. Hear Res. 2015;322:67–76.
[12] P. Arauz, S. L., Atlas, M., Baumgartner, W. D., Caversaccio, M., Chester-Browne, R., et al. (2016). Electrically evoked compound action potentials are different depending on the site of cochlear stimulation. Cochlear Implants Int. 17, 251–262. doi: 10.1080/14670100.2016.1240427
[13] Pourjavid A, Adel Ghahraman M, Sedaie M, Emamjome HA, Mobedshahi F, Abbasalipour Kabirrah P: Amplitude changes of the electrically evoked compound action potential in children with cochlear implants: preliminary results. Iran J Pediatr 2011;21:390-394.
[14] I. Akhoun, C.M. McKay, W. El-deredyElectrically evoked compound action potential artifact rejection by independent component analysis: technique validation Hear. Res., 302 (2013), pp. 60-73.

[15] Adenis V., Gourévitch B., Mamelle E., Recugnat M., Stahl P., Gnansia D., Nguyen Y., Edeline JM. “ECAP growth function to increasing pulse amplitude or pulse duration demonstrates large inter-animal variability that is reflected in auditory cortex of guinea pig”, PLoS ONE, DOI: 10.1371/journal.pone.0201771. 2018.
[16] N. Verma, A. Shoeb, J. Bohorquez, J. Dawson, J. Guttag, and A. P. Chandrakasan, "A micro-power EEG acquisition SoC with integrated feature extraction processor for a chronic seizure detection system," IEEE J. Solid-State Circuits, vol. 45, num. 4, pp. 804-816, Apr. 2010.
[17] M. S. J. Steyaert, W. M. C. Sansen, and C. Zhongyuan, “A micropower low-noise monolithic instrumentation amplifier for medical purposes,” IEEE J. Solid-State Circuits, vol. 22, no. 6, pp. 1163–1168, Dec. 1987.
[18] R. R. Harrison, C. Charles, "A low-power low-noise CMOS amplifier for neural recording applications," IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 958-63965, June 2003.
[19] R. R. Harrison, P. T. Watkins, R. J. Kier, R. O. Lovejoy, D. J. Black, B. Greger, and F. Solzbacher, “A low-power integrated circuit for a wireless 100-electrode neural recording system,” IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 123-133, Jan. 2007.
[20] X. Zou, W. S. Liew, L. Yao, and Y. Libin, "A 1V 22uW 32-channel implantable EEG recording IC," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 126-127, Feb. 2010.
[21] M. Azin, D. J. Guggenmos, S. Barbay, R. J. Nudo, and P. Mohseni, "A battery-powered activity-dependent intracortical microstimulation IC for brain-machine-brain interface," IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 731-745, Apr. 2011.

[22] F. Heer, S. Hafizovic, W. Franks, T. Ugniwenko, A. Blau, C. Ziegler,and A. Hierlemann, “CMOS microelectrode array for bidirectional interaction with neuronal networks,” Proceedings of the 31st European Solid-State Circuits Conference, pp. 335–338, Sept. 2005.
[23] Anh Tuan Do, YungSern Tan, Chunkit Lam, Minkyu Je and Kiat Seng Yeo, “Low power implantable neural recording front-end,” in Proc. SoC Design Conf. (ISOCC), Jeju Island ,2012, pp. 387-390.
[24] I.S. Jacobs and C.P. Bean, Fine particles, thin films and exchange anisotropy,
New York, Schenectady.
[25] D. Wheatley and T. Lehmann, "Electrically evoked compound action potential (ECAP) low-power low-noise CMOS amplifier," in Proc. Mid-West Symp. Circuits Syst., Montréal, Aug. 2007, pp. 41-4.
[26] S. Pavan, N. Krishnapura and P. Sankar, “A power optimized continuous-time ΔΣ ADC for audio applications” IEEE J. Solid-State Circuits, vol. 43, no. 2, pp. 351-360, Feb., 2008.
[27] P.-W. Chen, “The Design of an 8-Channel Analog Front-End with Chopper Modulated Amplifier and Fully Differential Hybrid SAR ADC in 65nm CMOS Technology for EEG Acquisition,” National Chiao Tung University, unpublished master degree’s dissertation.
[28] C. C Enz, F. Krummenacher, and E.A. Vittoz, “An Analytical MOS Transistor Model Valid in ALL Regions of Operation and Dedicated to Low-Voltage and Low-Current Applications”, Analog Integrated Circuits and Signal Processing Journal on Low-Voltage and Low-Power Design 8, pp. 83-114, July 1995.
[29] Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor, 3rd ed., Oxford University Press, 2011.

[30] C.-Y. Wu, and C.-S. Ho, “An 8-channel Chopper-Stabilized Analog Front-End Amplifier for EEG Acquisition in 65-nm CMOS,” in Proc. Asian Solid-State Circuits Conf., Nov. 2015, pp. 1-4.
[31] J. Rmírez-Angulo, R. G. Carvajal, J. A. Galán, and A. López-Martín, “A free but efficient low-voltage class-AB two-stage operational amplifier,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 7, pp.568–571, July 2006.
[32] J.-P. Hou, “The Design of a Fully Differential Bypass Window Successive Approximation Register Analog-to-Digital Converter and an Electrode-Tissue Impedance Measurement Circuit for Cochlear Implants,” National Chiao Tung University, unpublished master degree’s dissertation.
[33] Q. Fan, F. Sebastiano, J. H. Huijsing, and K. A. A. Makinwa, “A 1.8 µW 60 nV/rtHz capacitively-coupled chopper instrumentation amplifier in 65nm CMOS for wireless sensor nodes,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1534-1543, July 2011.
[34] C.-Y. Wu, and C.-S. Ho, “An 8-channel Chopper-Stabilized Analog Front-End Amplifier for EEG Acquisition in 65-nm CMOS,” in Proc. Asian Solid-State Circuits Conf., pp. 1-4, Nov. 2015.
[35] J. Yoo, et al., “An 8-channel scalable EEG acquisition SoC with patient-specific seizure classification and recording processor,” IEEE J. Solid-State Circuits, vol. 48, no. 1, pp. 214-228, Jan. 2013.
[36] T. Denison, K. Consoer, W. Santa, A. T. Avestruz, J. Cooley, and A. Kelly, “A 2 µW 100 nV/rtHz chopper stabilized instrumentation amplifier for chronic measurement of neural field potentials,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2934-2945, Dec. 2007.


[37] P.-W. Chen, C.-W. Huang and C.-Y. Wu, “An 1.97μ, W/Ch 65nm-CMOS 8-Channel Analog Front-End Acquisition Circuit with Fast-Settling Hybrid DC Servo Loop for EEG Monitoring,” in Proc. Int. Symp. Circuits Syst. (ISCAS), Florence, May 2018, pp. 1-5.
[38] M. Daliri and M. Maymandi-Nejad, “Ultra-low voltage common-mode voltage detector circuit,” IEEE Electron. Letters, vol. 44, no. 13, pp. 782-783, June 2008.
[39] R. Wu, K. A. A. Makinwa, and J. H. Huijsing, “A Chopper Current-Feedback Instrumentation Amplifier with a 1mHz 1/f Noise corner and an AC-Couple Ripple Reduction Loop,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3232–3243, Dec. 2009.
[40] Z. Luo, D. Ker, Y. Yang, and H. Cheng, “A digitally dynamic power supply technique for 16 channel 12 V tolerant stimulator realized in a 0.18 μm 1.8 V/3.3 V low voltage CMOS process,” IEEE Trans. Biomed. Circuits Syst., vol. 11, no. 5, pp. 1087 1096, Oct. 2017.
[41] C.-H. Chung, “The Design of two Low Power 10-Bit/12-Bit 100-KS/s Hybrid/Split-Capacitor SAR ADCs and an Electrode-Tissue Impedance Measurement Circuit for Implantable Medical SoC Integration,” National Chiao Tung University, unpublished master degree’s dissertation.
[42] 307 training. [Online]. http://www.alab.ee.nctu.edu.tw/wpmu/ed307.
連結至畢業學校之論文網頁點我開啟連結
註: 此連結為研究生畢業學校所提供,不一定有電子全文可供下載,若連結有誤,請點選上方之〝勘誤回報〞功能,我們會盡快修正,謝謝!
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top
無相關論文
 
無相關期刊
 
1. 用於植入式生醫晶片系統整合之低功率十位元/十二位元每秒十萬次取樣混合型/電容分裂型逐次漸進式類比數位轉換器與電極組織阻抗量測電路
2. 應用於人工耳蝸差動視窗逐次漸進式類比數位轉換器與電極組織阻抗量測電路設計
3. 應用於下視網膜植入具電荷泵升壓電路之雙向共用電極180奈米互補式金氧半256像素感測及雙向電流刺激晶片設計
4. 應用於醫療腦電訊號截取之八通道互補式金氧半類比前端放大器與經顱直流電刺激之腦電訊號系統設計
5. 應用於局部場電位訊號紀錄之六十五奈米互補式金氧半八通道耐受正負六伏特共模雜訊與正負十毫伏特差模雜訊之類比前端生理訊號截取電路設計
6. 應用於下視網膜植入具電荷泵升壓電路之180奈米互補式金氧半光伏供電256像素感測及雙向刺激晶片設計
7. 應用於帕金森症閉迴路深部腦刺激具雜訊去除電路之四通道互補式金氧半類比前端放大器設計
8. 應用於植入式生醫元件之互補式金氧半 13.56-MHz 具有低功率脈衝式負載鍵移調變電路和被動相位鍵移調變器之功率與雙向數據遙測系統設計
9. 應用於植入式生醫元件之互補式金氧半13.56-MHz高效率主動式正負一倍壓整流器及直流穩壓器之設計
10. 應用於人工耳蝸電誘發複合活動電位擷取及電極組織阻抗量測之互補式金氧半類比前端電路之設計
11. 應用於人體癲癇與帕金森氏症治療之互補式金屬氧化物半導體積體電路系統單晶片與閉迴路神經調控系統設計
12. 應用於下視網膜植入具閉迴路電荷泵升壓電路與雙向共用電極180奈米互補式金氧半自動適應光源256像素感測及雙向電流刺激晶片之設計
13. 光伏供電下視網膜晶片電極架構與影像動態範圍之改進設計及其植入應用
14. 應用於植入式人工耳蝸之13.56-MHz互補式金氧半電感耦合電源與晶片系統設計與分析
15. 應用於脊髓神經訊號記錄之四通道互補式金氧半類比前端生理訊號截取電路