臺灣博碩士論文加值系統

我們提出了一個製程非常簡單且完全相容於現有CMOS製程技術的新穎性元件，我們稱它為源極抬高式電晶體(Source-Top MOSFET, STMOSFET)，並且應用於無電容式單電晶體動態隨機存取記憶體(Capacitor-less One Transistor Dynamic Random Access Memory, 1T-DRAM )。利用新穎架構向上延伸的源極抬高區域，使其不僅能在有限的面積之下，達到長通道的效果，而且汲極高電場不會侵入到垂直通道的部份，因此可以有效抑制短通道效應，增強閘極控制力。除此之外因源極抬高的架構，可以在不增加面積的前提下，我們得到了足夠大的假中性區域來進行電荷的儲存，且因電荷儲存區也遠離汲極的高電場，因此累積的電洞不容易受到汲極電場的擾動，這都使記憶體特性可程式規劃窗(Programming Window, PW)與資料儲存時間(Retention Time, RT)大大的提升，與傳統1T-DRAM比較之下分別改善為56.43 %與56.63 %。再者，汲極端仍保有超薄本體架構，電流特性跟傳統全空乏式矽覆絕緣(Fully Depleted Silicon on Insulator, FD-SOI)元件有相同的優點，P-N接面也大大減少。最後，因為源極與汲極不在同一水平面上，可以減少空乏區相互接觸的機會，所以可以有效減輕發生穿透效應的機會(Punch through effect)。
另一方面，我們也將源極抬高式電晶體做進一步改良。由於改變製程步驟便可以使兩側的閘極同時形成，我們稱為源極抬高式雙閘極電晶體(Double-Gate MOSFET with Source-Top, STDG MOSFET)，此雙閘極架構也有源極抬高式電晶體的各項優點。在源極抬高式雙閘極電晶體基本特性方面，有優秀的DIBL值(28.98 mV/V)與次臨界擺幅(66.95 mV/dec)之元件；在作為超小尺寸之1T-DRAM，可得到可程式規劃窗與資料儲存時間最大值分別為178.63 μA/μm與57.84 ms的記憶體元件。相較於其他研究團隊，其可程式規劃窗有相當優秀的表現。

We propose novel 1T-DRAM cells with raised source structure. The cell using the raised source region can achieve the characteristics of long gate length one in a limited area. And, it can suppress short channel effects because the electric field of drain encroaches to vertical channel decreasingly. All these methods can improve the gate controllability. In addition, the raised source region possesses a larger data storage region without increasing the device area. Besides, the programming window can be improved 56.43 % compared with the conventional planar MOSFET, and the retention time can also be improved 56.63 %. Besides, the drain side still maintains the advantages of ultra-thin body structure, and the area of P-N junction is reduced greatly. Finally, since the raised source structure, the drain and source depletion regions of the cell could not to be contacted together easily so that the device does not appear punch through effect even the high drain bias is applied.
On the other hand, we also propose the double-gate MOSFET with source-top structure simultaneously. We name it as the STDG MOSFET. By controlling the bias of the second gate, we can operate the device as a MOSFET or the 1T-DRAM friendly. Be a MOSFET, the device exhibits excellent SS = 66.95 mV/dec and DIBL = 28.98 mV/V. Whileas, be a 1T-DRAM we find the maximum value of the programming window (178.63 μA/μm) and the retention time (57.84 ms). STDG MOSFET has excellent programming window compared with those done by the other research teams.

論文審定書....................................................................................................i
英文論文審定書...........................................................................................ii
致謝..............................................................................................................iii
摘要..............................................................................................................iv
Abstract.........................................................................................................v
第一章 導論 1
1.1 研究背景 1
1.2 1T-DRAM之論文探討 7
1.3 動機 13
第二章 操作原理 15
2.1 浮體效應 15
2.2 1T-DRAM之操作機制 17
2.2.1 撞擊游離機制 17
2.2.2 閘極引致汲極漏電流寫入機制 20
2.2.3 BJT讀取機制 23
第三章 元件製作 25
3.1 源極抬高式架構理想模擬製程 25
3.1.1 源極抬高式電晶體 25
3.1.2 源極抬高式雙閘極電晶體 25
3.2 模擬元件架構尺寸說明 28
3.3 實際元件製作 29
第四章 研究方法與結果討論 33
4.1 研究方法 33
4.2 記憶體特性之定義 36
4.2.1 可程式規劃窗(Programming Window) 36
4.2.2 資料儲存時間(Data Retention Time) 37
4.3 源極抬高式電晶體架構之探討 38
4.3.1 源極抬高式電晶體之基本特性分析 39
4.3.2 源極抬高式電晶體之記憶體特性分析 44
4.4 源極抬高式電晶體與傳統SOI電晶體之特性分析 51
4.4.1 源極抬高式電晶體與傳統SOI電晶體之特性探討(相同元件面積) 51
4.4.2 源極抬高式電晶體與傳統SOI電晶體之特性探討(相同通道長度) 74
4.5 源極抬高式雙閘極電晶體架構之探討 87
4.5.1 源極抬高式雙閘極電晶體之基本特性分析 87
4.5.2 源極抬高式雙閘極電晶體之記憶體特性分析 94
4.6 近年各1T-DRAM論文之記憶體特性探討 110
4.7 元件實作結果與量測 112
第五章 結論與未來發展 115
5.1 結論 115
5.2 未來展望 117
參考文獻 118
論文著述 126
個人得獎 129

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