臺灣博碩士論文加值系統

傳統上連續時間主動濾波器的設計，往往需要在低電壓與高動態範圍間有所取捨，解決這個問題的方法便是利用壓擴(Companding)這項技術。目前可以實現的方式大致可分成兩類，ㄧ者為利用BJT工作在飽和區的i-v指數關係，但為了降低成本，並且整合數位與類比電路,另一利用 CMOS製程來實現的被開發出來。本計劃將利用整合CMOS製程中寄生的垂直式BJT來設計一個全新的ㄧ階低通對數濾波器。與傳統對數濾波器相比，本電路擁較高的工作頻率。

在本研究計畫中我們先採用Hspice 來模擬對數濾波器的諸多特性，以確保該電路設計的準確性及作為設計佈局的參考。在完整的模擬與分析之後，將使用0.35um CMOS 製程製作晶片。

Traditionally, the design of continuous time active filters usually has a trade offbetween low-voltage and high dynamic range. One way to solve this problem is companding technology. There are two methods for companding filters. The first method utilizes the
exponential I-V characteristics of BJT in the saturation region. In order to reduce the cost andintegrate the analog and digital circuits, the other method was exploited using CMOS process. In this project, a new first-order low pass log-domain filter based on CMOS parasitic vertical BJTwill be proposed. This filter has higher frequency response than previous circuits.

We will first employ Hspice to simulate the log-domain filter to ensure the correctness of the circuit and make it a reliable reference with the circuit layout. After summarizing all the simulations and analyses, the chip will be fabricated with 0.35um CMOS technology.

Contents
Abstract
Chapter 1 Introduction 1
1.1 Background 1
1.2 Motivation 3
1.3 Overview of the Thesis 4
Chapter 2 Previous Log-domain Filters 5
2.1 Companding Techniques 5
2.2 Previous Log-domain Filters 7
2.2.1 Frame of Log-domain Circuit 7
2.2.2 Log-domain Circuits 11
Chapter 3 The Proposed Circuit 19
3.1 State-Space Analysis 19
3.1.1 Basic Equations 19
3.1.2 Derivation of First Order Filter 20
3.2 Bipolar Junction Transistors in Standard CMOS Process 23
3.2.1 The Vertical PNP Transistor 23
3.3 The Proposed Log-domain Filter 27
3.3.1 The Proposed Log Filter 27
3.3.2 Analysis of Sub Circuits 29
3.4 Transfer Function 32
Chapter 4 Simulation and Measurement 36
4.1 The Circuit Implement, Layout& Specifics 36
4.2 Simulation & Results 39
4.2.1 Testing method & Measurement circuit 39
4.2.2 Frequency Response 41
4.2.3 Tunable Range & Total Harmonic Distortion (THD) 44
4.2.4 Comparisons 46
Chapter 5 Conclusion 48
References 49

List of Figure
Fig. 1.1 Ratio of power dissipation and dynamic range in traditional and companding filter 2
Fig. 2.1 Output RMS signal and noise versus input RMS signal for signal process with (a) wide and (b) narrow usable dynamic range 6
Fig. 2.2 Signal domains in companding processing 6
Fig. 2.3 Companding Filter Function Block 7
Fig. 2.4 Adams’s Log Filter Circuit 8
Fig. 2.5 BJT Log-Domain Filter 11
Fig. 2.6 Second-order low pass filter schematic [5] 12
Fig. 2.7 CMOS Log Filter Structure 13
Fig. 2.8 Schematic of biquadratic low-pass log-domain filter [14] 14
Fig. 2.9 Block diagram [17] 16
Fig. 2.10 Log-domain 2nd-order Butterworth filter [17] 17
Fig. 3.1 The physical structure and circuit equivalent V Q is the vertical PNP L Q is the lateral PNP in N-well CMOS process 24
Fig. 3.2 Physical structure of Vertical Bipolar Junction in N-Well standard CMOS process24
Fig. 3.3 Top view of Vertical Bipolar Junction Layout in N-Well standard CMOS process 25
Fig. 3.4 The whole Log-Domain Filter 27
Fig. 3.5 Core of filter 29
Fig. 3.6 Output circuit 31
Fig. 4.1 The layout of the low pass Log-domain filter 36
Fig. 4.2 The whole chip of the filter 37
Fig. 4.3 The photograph of the chip 38
Fig. 4.4 Proposed the filter’s measurement circuit 39
Fig. 4.5 Frequency response under different conditions 41
Fig. 4.6(a) The Frequency response C=40pF the Idc =20μA and 60μA 42
Fig. 4.6(b) The Frequency response C=20pF the dc I =20μA and 60μA 43
Fig. 4.6(c) The Frequency response C=10pF the dc I =20μA and 60μA 43
Fig. 4.7 Frequency tuning range 44
Fig. 4.8 (a) THD C=20pF 45
Fig. 4.8 (b) THD C=10pF 45
List of Table
Table 3.1 List of the layout description 25
Table 4.1 Specifics of the first order Log-domain filter 37
Table 4.2 Comparison between simulation results and measurement results 46
Table 4.3 Comparison with other type log domain filter 47

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