臺灣博碩士論文加值系統

本篇論文提出一個應於0.5V全數位鎖相迴路的電壓源靈敏度補償機制，此設計包含三大部分：全數位鎖相迴路、4-bit可調式補償電路以及數位偵測電路。本補償機制設計為Foreground執行，意即在每次電源開啟時執行偵測以尋找最佳化補償值，而本機制利用全數位鎖相迴路中部份元件即可達成簡單粗略的抖動偵測並依此結果來完成搜尋，當搜尋完成數位偵測電路將關閉避免多餘功耗產生。全數位鎖相迴路操作電壓為0.5伏特，輸出頻率為400MHz，時脈抖動為74ps，功率消耗為120.3uW。當電壓源雜訊為峰對峰值10mV頻率10kH的正弦波時，時脈抖動為370ps，經過補償後時脈抖動為101.9ps。此晶片使用TSMC 90nm 1P9M製程實現，晶片佈局面積為0.438 mm^2。

This thesis proposes a supply sensitivity compensation scheme for a 0.5V all-digital phase-locked loop. This design includes an ADPLL, a 4-bit adjustable compensation circuit, and a digital detect circuit. The compensation scheme is designed for foreground execution, which means it detects and finds the best compensation value every time when the power is on. The scheme uses some components of the ADPLL to do jitter measure and follow the result to search the compensation value. After the search is complete, the detection circuit is shut sown to avoid unnecessary power consumption. The power consumption of the ADPLL is 120.3uW for a supply voltage of 0.5V and an operating frequency of 400MHz. It’s peak-to-peak jitter is 74ps. For a noise of 10mV 10kHz sinusoidal waveform on the supply voltage, the peak to peak jitter without and with compensation are 370ps and 101.9ps. This chip will be fabricated in TSMC 90nm 1P9M process, with an area of 0.438 mm^2.

摘 要 i
Abstract ii
誌謝 iii
目錄 iv
表目錄 viii
圖目錄 ix
第一章 1
緒論 1
1.1簡介 1
1.2研究動機 2
1.3論文結構 3
第二章 4
鎖相迴路原理與文獻 4
2.1前言 4
2.2類比式鎖相迴路 5
2.3數位式鎖相迴路 7
2.3.1 相位頻率偵測器 8
2.3.2 充電幫浦 9
2.3.3 迴路濾波器 10
2.3.4 壓控振盪器 11
2.4全數位式鎖相迴路 12
2.5迴路分析 13
2.6文獻回顧 15
2.6.1 An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillator[1] 15
2.6.2 A 0.4-to-3 Ghz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration [2] 17
2.6.3 文獻回顧總結 19
第三章 20
電壓源靈敏度補償電路和機制 20
3.1前言 20
3.2鎖相迴路雜訊分析 20
3.3補償機制架構與流程 23
3.4 4-BIT可調式補償電路 24
3.5數位偵測電路 26
3.5.1 抖動定義 26
3.5.2 鎖定偵測器與抖動累加器 28
3.5.3 循序搜尋電路 31
第四章 33
全數位鎖相迴路架構 33
4.1系統架構 33
4-2全數位鎖相迴路系統分析 34
4.2.1 全數位鎖相迴路S平面模型 34
4.2.2 數位迴路濾波器參數計算 36
4.3全數位鎖相迴路子電路介紹 38
4.3.1相位頻率偵測器&;相位選擇器 38
4.3.2時間數位轉換器 39
4.3.3數位控制振盪器 40
4.3.3三角積分調變器 43
第五章 46
模擬結果、晶片佈局、量測考量 46
5.1模擬結果 46
5.1.1 MATLAB行為模擬 47
5.1.2 HSPICE模擬 48
5.2晶片佈局圖 54
5.3量測考量 56
5.4電路規格 58
5.5文獻比較 58
第六章 60
結論 60
參考文獻 62

[1] T. Wu, K. Mayaram, and U.K. Moon, "An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators," IEEE Journal of Solid-State Circuits, vol.42, no.4, pp.775,783, April 2007
[2] A. Elshazly, R. Inti, W. Yin, B. Young, and P.K. Hanumolu, "A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration," IEEE Journal of Solid-State Circuits, vol.46, no.12, pp.2759,2771, Dec. 2011
[3] V. Kratyuk, P.K. Hanumolu, U.K. Moon, and K. Mayaram, "A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy," IEEE Transactions on Circuits and Systems II: Express Briefs, vol.54, no.3, pp.247,251, March 2007
[4] S.Y. Lin, and S.I. Liu, "A 1.5 GHz All-Digital Spread-Spectrum Clock Generator," IEEE Journal of Solid-State Circuits, vol.44, no.11, pp.3111,3119, Nov. 2009
[5] P. Dudek, S. Szczepanski, and J.V. Hatfield, "A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line," IEEE Journal of Solid-State Circuits, vol.35, no.2, pp.240,247, Feb. 2000
[6] Y.C. Ho, Y.S. Yang, and C.C. Su, "A 0.2–0.6 V ring oscillator design using bootstrap technique," IEEE Asian Solid State Circuits Conference, vol., no., pp.333,336, Nov. 2011
[7] S.Y. Kao, and S.I. Liu, "A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression," IEEE Transactions on Very Large Scale Integration Systems, vol.19, no.4, pp.592,602, April 2011
[8] C.M. Lai, M.H. Shen, Y.D. Wu, K.H. Huang, and P.C. Huang, "A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS," IEEE International Symposium on Circuits and Systems, pp.981,984, May 2011
[9] Y.S. Park, and W.Y. Choi, "On-Chip Compensation of Ring VCO Oscillation Frequency Changes Due to Supply Noise and Process Variation," IEEE Transactions on Circuits and Systems II: Express Briefs, vol.59, no.2, pp.73,77, Feb. 2012
[10] X.Y. Deng, J. Yang, and J.H. Wu, "Low jitter ADPLL insensitive to power supply noise," IEEE International Conference on Industrial Technology, pp.1050,1054, March 2010
[11] C.F. Tsai, W.J. Li, P.Y. Chen, Y.Z. Lin, and S.J. Chang, "On-chip reference oscillators with process, supply voltage and temperature compensation," International Symposium on Next-Generation Electronics, pp.108,111, Nov. 2010
[12] T. Xia, S. Wyatt, and R. Ho, "Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration," IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.12,19, Oct. 2006
[13] E. Alon, J. Kim, S. Pamarti, K. Chang, and M. Horowitz, "Replica compensated linear regulators for supply-regulated phase-locked loops," IEEE Journal of Solid-State Circuits, vol.41, no.2, pp.413,424, Feb. 2006
[14] B.M. Moon, H.P. Chan, and D.K. Jeong, "Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation," IEEE Transactions on Circuits and Systems II: Express Briefs, vol.55, no.10, pp.1036,1040, Oct. 2008
[15] F. Herzel, and B. Razavi, "A study of oscillator jitter due to supply and substrate noise," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol.46, no.1, pp.56,62, Jan 1999
[16] S. Dosho, N. Yanagisawa, and A. Matsuzawa, "A background optimization method for PLL by measuring phase jitter performance," IEEE Journal of Solid-State Circuits, vol.40, no.4, pp.941,950, April 2005
[17] S. Hoppner, S. Haenzsche, S. Hartmann, S. Schiefer, and R. Schuffny, "Temperature and supply voltage compensated biasing for digitally controlled oscillators," International Conference Mixed Design of Integrated Circuits and Systems, pp.283,288, May 2012
[18] 劉深淵、楊清淵，鎖相迴路，滄海書局，2005年。
[19] 高曜煌，射頻鎖相迴路IC設計，滄海書局，2011年。