|
[1]D. Kahng and M. M. Atalla, “Silicon-silicon Dioxide Field Induced Surface Devices,” in IRE-AIEE Solid-state Device Res. Conf., (Carnegie Inst. of Technol., Pittsburgh, PA), 1960. [2]International Technology Roadmap for Semiconductors (ITRS): 2012, Semiconductor Industry Association (SIA), Available: www.itrs.net/. [3]D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor, and C. Hu, “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320–2325, Dec. 2000. [4]S. W. Huang and J. G. Hwu, “Electrical Characterization and Process Control of Cost Effective High-k Aluminum Oxide Gate Dielectrics Prepared by Anodization Followed by Furnace Annealing,” IEEE Trans. Electron Devices, vol. 50, no. 7, pp. 1658–1664, Jul. 2003. [5]C. S. Kuo, J. F. Hsu, S. W. Huang, L. S. Lee, M. J. Tsai, and J. G. Hwu, “High-k Al2O3 Gate Dielectrics Prepared by Oxidation of Aluminum Film in Nitric Acid Followed by High Temperature Annealing,” IEEE Trans. Electron Devices, vol. 51, no. 6, pp. 854–858, Jun. 2004. [6]S. W. Huang and J. G. Hwu, “Lateral Nonuniformity of Effective Oxide Charges in MOS Capacitors with Al2O3 Gate Dielectrics,” IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1608–1614, Jul. 2006. [7]B. H. Lee, S. C. Song, R. Choi, and P. Kirsch, “Metal Electrode/High-k Dielectric Gate-Stack Technology for Power Management,” IEEE Trans. Electron Device, vol. 55, no. 1, pp. 8–20, Jan. 2008. [8]J. Y. Cheng, H. T. Lu, and J. G. Hwu, “Metal-oxide-semiconductor Tunneling Photodiodes with Enhanced Deep Depletion at Edge by High-k Material,” Appl. Phys. Lett., vol. 96, no. 23, pp. 233506-1–233506-3, June 2010. [9]J. Y. Cheng and J. G. Hwu, “Characterization of Edge Fringing Effect on the C–V Responses From Depletion to Deep Depletion of MOS(p) Capacitors With Ultrathin Oxide and High-κ Dielectric,” IEEE Trans. Electron Devices, vol. 59, no. 3, pp. 565–572, Mar. 2012. [10]P. L. Hsu, “Edge-Dependent I-V Behavior of MOS Structures with Ultrathin Oxides under Inversion Region,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 2013. [11]P. F. Schmidt and W. Michel, “Anodic Formation of Oxide Films on Silicon,” J. Electrochem. Soc., vol. 104, pp. 230, 1957. [12]V. Parkhutik, “New Effects in the Kinetics of the Electrochemical Oxidation of Silicon,” Electrochim. Acta, vol. 45, pp. 3249–3254, 2000. [13]M. Grecea, C. Rotaru, N. Nastase, and G. Craciun, “Physical Properties of SiO2 Thin Films Obtained by Anodic Oxidation,” J. Mol. Struct., pp. 607–610, 1999. [14]D. Gong, C. A. Grimes, O. K. Varghese, W. Hu, R. S. Singh, Z. Chen, and E. C. Dickey, “Titanium Oxide Nanotube Arrays Prepared by Anodic Oxidation,” J. Mater. Res., vol. 16, no. 12, pp. 3331–3334, Dec. 2001. [15]Ch. Comninellis and C. Pulgarin, “Anodic Oxidation of Phenol for Waste Water Treatment,” J. Appl. Electrochem., vol. 21, no. 8, pp. 703–708, Aug. 1991. [16]C. C. Ting, Y. H. Shih, and J. G. Hwu, “Ultralow Leakage Characteristics of Ultrahthin Gate Oxides (~3 nm) Prepared by Anodization Followed by High-Temperature Annealing,” IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 179–181, 2002. [17]M. J. Jeng, “Application of Anodic Oxidation and Rapid Thermal Treatment on Thin Gate Oxides and Radiatoin-Hardness CMOS sensing circuit,” Ph.D. dissertation, Dept. Elect. Eng., Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 1996. [18]S. K. Ghandhi, VLSI Fabrication Principles, 2nd ed., Wiley-Interscience, pp. 487–495, 1994. [19]E. H. Nicollian and J. R. Brews, MOS Physics and Technology, New York: Wiley, pp. 74, 1981. [20]K. Yang, C. Hu, “MOS Capacitance Measurements for High-Leakage Thin Dielectrics,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1500–1501, July 1999. [21]K. Yang, Y. C. King, and C. Hu, “Quantum Effect in Oxide Thickness Determination from Capacitance Measurement,” in Symp. VLSI Tech. Dig., pp. 77–78, 1999. [22]Berkeley Device Group, Available: www-device.eecs.berkeley.edu/qmcv/. [23]D. J. Griffiths, Introduction to Quantum Mechanics, 2nd ed., Pearson Prentice Hall, pp. 322, 2004. [24]A. Ghetti, C. T. Liu, M. Mastrapasqua, and E. Sangiorgi, “Characterization of Tunneling Current in Ultrathin Gate Oxide,” Solid State Electron., vol. 44, no. 9, pp. 1523–1531, Sep. 2000. [25]T. Y. Chen, “Process Development and Characterization of MOS Capacitor with Ultra-thin Oxide,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 2011. [26]N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, “Modeling Study of Ultrathin Gate Oxides Using Direct Tunneling Current and Capacitance–Voltage Measurements in MOS Devices,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1464–1471, July 1999. [27]W. C. Lee and C. Hu, “Modeling CMOS Tunneling Currents Through Ultrathin Gate Oxide Due to Conduction- and Valence-Band Electron and Hole Tunneling,” IEEE Trans. Electron Devices, vol. 48, no. 7, pp. 1366–1373, July 2001. [28]F. Li, S. P. Mudanai, Y. Y. Fan, L. F. Register, and S. K. Banerjee, “Physically Based Quantum–Mechanical Compact Model of MOS Devices Substrate-Injected Tunneling Current Through Ultrathin (EOT ~ 1 nm) SiO2 and High-κ Gate Stacks,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1096–1106, May 2006. [29]Y. P. Lin and J. G. Hwu, “Oxide-Thickness-Dependent Suboxide Width and Its Effect on Inversion Tunneling Current,” J. Electrochem. Soc., vol. 151, no. 12, pp. G853–G857, Oct. 2004. [30]C. W. Lee, “A Comprehensive Quantum-Mechanical Model for C-V and I-V Characteristics in Ultrathin MOS Structure and Experimental Verification,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 2013. [31]R. Tsu and L. Esaki, “Tunneling in a Finite Superlattice,” Appl. Phys. Lett., vol. 22, no. 11, pp. 562, Mar. 1973. [32]SILVACO Inc., ATLAS User’s Manual, Oct. 2013. [33]R. N. Hall, “Electron-Hole Recombination in Germanium,” Phys. Rev., vol. 87, no.2, pp. 387, July 1952. [34]W. Shockley and W. T. Read, “Statistics of the Recombinations of Holes and Electrons,” Phys. Rev., vol. 87, no. 5, pp. 835–842, Sep. 1952. [35]J. Dziewior and W. Schmid, “Auger Coefficients for Highly doped and Highly Excited Silicon,” Appl. Phys. Lett., vol. 31, no. 5, pp. 346–348, Sep. 1977. [36]J. W. Slotboom and H. C. de Graaff, “Measurements of Bandgap Narrowing in Si Bipolar Transistors,” Solid-State Electron., vol. 19, no. 10, pp. 857–862, Oct. 1976. [37]M. Lundstrom, Fundamentals of Carrier Transport, 2nd ed., Cambridge University Press, 2009. [38]S. Datta, Electronic Transport in Mesoscopic Systems, 1st ed., Cambridge University Press, 1995. [39]S. Altindal, I. Dokme, M. M. Bulbul, N. Yalcin, and T. Serin, “The Role of the Interface Insulator Layer and Interface States on the Current-transport Mechanism of Schottky Diodes in Wide Temperature Range,” Microelectron. Eng., vol. 83, no. 3, pp. 499–505, Mar. 2006. [40]I. Dokme, S. Altindal, “On the Intersecting Behaviour of Experimental Forward Bias Current–voltage (I–V) Characteristics of Al/SiO2/p-Si (MIS) Schottky Diodes at Low Temperatures,” Semicond. Sci. Technol., vol. 21, no. 8, pp. 1053–1058, June. 2006. [41]T. Y. Chen and J. G. Hwu, “Two States Phenomenon in the Current Behavior of Metal-oxide-semiconductor Capacitor Structure With Ultra-thin SiO2,” Appl. Phys. Lett., vol. 101, no. 7, pp. 073506-1–073506-4, Aug. 2012. [42]C. H. Chen, K. C. Chuang, and J. G. Hwu, “Characterization of Inversion Tunneling Current Saturation Behavior for MOS(p) Capacitors With Ultrathin Oxides and High- k Dielectrics,” IEEE Trans. Electron Devices, vol. 56, no. 6, pp. 1262–1268, June 2009. [43]M. Y. Doghish and F. D. Ho, “A Comprehensive Analytical Model for Metal–Insulator–Semiconductor (MIS) Devices,” IEEE Trans. Electron Devices, vol. 39, no. 12, pp. 2771–2780, Dec. 1992. [44]J. Cai and C. T. Sah, “Gate Tunneling Currents in Ultrathin Oxide Metal-oxide-silicon Transistors,” J. Appl. Phys., vol. 89, no. 4, pp. 2272–2285, Feb. 2001. [45]F. Li, S. Mudanai, L. F. Register, and S. K. Banerjee, “A Physically Based Compact Gate C–V Model for Ultrathin (EOT ~ 1 nm and Below) Gate Dielectric MOS Devices,” IEEE Tran. Electron Devices, vol. 52, no. 6, pp. 1148–1158, June 2005. [46]C. H. Choi, J. S. Goo, T. Y. Oh, Z. Yu, R. W. Dutton, A. Bayoumi, M. Cao, P. V. Voorde, D. Vook, and C. H. Diaz, “MOS C–V Characterization of Ultrathin Gate Oxide Thickness (1.3–1.8 nm),” IEEE Electron Device Lett., vol. 20, no. 6, pp. 292–294, June 2009. [47]C. Y. Liu, B. Y. Chen, and T. Y. Tseng, “Deep Depletion Phenomenon of SrTiO3 Gate Dielectric Capacitor,” J. Appl. Phys., vol. 95, no. 10, pp. 5602–5607, May 2004. [48]S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFET’s,” IEEE Electron Device Lett., vol. 18, no. 5, pp. 209–211, May 1997. [49]C. S. Tan, K. N. Chen, and S. J. Koester, 3D Integration for VLSI systems, Pan Stanford, 2012. [50]E. E. Aktakka, N. Ghafouri, C. E. Smith, R.L. Peterson, M. M. Hussain, and K. Najafi, “Post-CMOS FinFET Integration of Bismuth Telluride and Antimony Telluride Thin-based Thermoelectric Devices on SOI Substrate,” IEEE Electron Device Lett., vol. 34, no. 10, pp. 1334–1336, Oct. 2013. [51]Y. H. Shih, S. R. Lin, T. M. Wang, and J. G. Hwu, “High Sensitive and Wide Detecting Range MOS Tunneling Temperature Sensors for On-chip Temperature Detection, ” IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1514–1521, Sept. 2004. [52]M. Sasaki, M. Ikeda, and K. Asada, “A Temperature Sensor with An Inaccuracy of-1/+0.8 °C Using 90-nm 1-V CMOS for Online Thermal Monitoring of VLSI Circuits,” IEEE T. Semiconduct. M., vol. 21, no. 2, pp. 201–208, May 2008. [53]K. M. Chao, W. C. Lee, W. Liu, X. Jin, P. Su, S. K. H. Fung, J. X. An, B. Yu, and C. Hu, “BSIM4 Gate Leakage Model Including Source-Drain Partition,” in IEDM Tech. Dig., 2000, pp. 815–818. [54]S. M. Sze, Physics of Semiconductor Devices, 3rd ed., John Wiley &; Sons, 2007. [55]Y. H. Shih and J. G. Hwu, “An On-chip Temperature Sensor by Utilizing a MOS Tunneling Diode,” IEEE Electron Device Lett., vol. 22, no. 6, pp. 299–301, June 2001. [56]C. H. Lin, B. C. Hsu, M. H. Lee, and C. W. Liu, “A Comprehensive Study of Inversion Current in MOS Tunneling Diode,” IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2125–2130, Sept. 2001. [57]C. Y. Wang and J. G. Hwu, “Characterization of Stacked Hafnium Oxide (HfO2) / Silicon Dioxide (SiO2) Metal-oxide-semiconductor (MOS) Tunneling Temperature Sensors,” J. Electrochem. Soc., vol.157, vo.10, pp. J324–J328, Oct. 2010. [58]M. du Plessis, H. Aharoni, and L. W. Snyman, “Silicon LEDs Fabricated in Standard VLSI Technology as Components for All Silicon Monolithic Integrated Optoelectronic Systems,” IEEE J. Sel. Top. Quant., vol. 8, no. 6, pp. 1412–1419, Nov. 2002. [59]K. Misiakos, E. Tsoi, E. Halmagean, and S. Kakabakos, “Monolithic Integration of Light Emitting Diodes, Detectors and Optical Fibers on a Silicon Wafers: a CMOS Compatible Optical Sensor,” in IEDM Tech. Dig., Dec. 1998. [60]V. Mohammadi, L.Qi, N. Golshani, C. K. R. Mok, W. B. de Boer, A. Sammak, J. Derakhshandeh, J. van der Cingel, and L. K. Nanver, “VUV/Low-energy Electron Si Photodiodes with Postmetal 400 °C PureB Deposition,” IEEE Electron Device Lett., vol. 34, no. 12, pp. 1545–1547, Dec. 2013. [61]C.W. Liu, W. T. Liu, M. H. Lee, W. S. Kuo, and B. C. Hsu, “A Novel Photodetector Using MOS Tunneling Structures,” IEEE Electron Device Lett., vol. 21, no. 6, pp. 307–309, June 2000. [62]A. El Gamal and H. Eltoukhy, “CMOS Image Sensors,” IEEE Circuits Devices Mag., vol. 21, no. 3, pp. 6–20, June 2005. [63]C. H. Lin and C. W. Liu, “Metal-insulator-semiconductor Photodetectors,” Sensors, vol. 10, no. 10, pp. 8797–8826, Sep. 2010. [64]S. Morita, A. Shinozaki, Y. Morita, K. Nishimura, T. Okazaki, S. Urabe and M. Morita, “Tunneling Current through Ultrathin Silicon Dioxide Films under Light Exposure,” Jpn. J. Appl. Phys., vol. 43, no. 11, pp. 7857–7860, Nov. 2004. [65]B. C. Hsu, S. T. Chang, T. C. Chen, P. S. Kuo, P. S. Chen, Z. Pei, and C. W. Liu, “A High Efficient 820 nm MOS Ge Quantum Dot Photodetector,” IEEE Electron Device Lett., vol. 24, no. 5, pp. 318–320, May 2003. [66]J. Y. Cheng and J. G. Hwu, “Characterization of Edge Fringing Effect on the C-V Responses from Depletion to Deep Depletion of MOS(p) Capacitors with Ultrathin Oxide and High-κ Dielectric,” IEEE Trans. Electron Devices, vol. 59, no. 3, pp. 565–572, Mar. 2012. [67]B. C. Hsu, C. W. Liu, W. T. Liu, and C. H. Lin, “A PMOS Tunneling Photodetector,” IEEE Trans. Electron Devices, vol. 48, no. 8, pp. 1747–1749, Aug. 2001. [68]B. E. Coss, W. Y. Loh, R. M. Wallace, J. Kim, P. Majhi, and R. Jammy, “Near Band Edge Schottky Barrier Height Modulation Using High-κ Dielectric Dipole Tuning Mechanism,” Appl. Phys. Lett., vol. 95, no. 22, pp. 222105-1–222105-3, Dec. 2009. [69]M. Y. Doghish and F. D. Ho, “A Comprehensive Analytical Model for Metal-insulator-semiconductor (MIS) Devices: a Solar Cell Application,” IEEE Trans. Electron Devices, vol. 40, no. 8, pp. 1446–1454, Aug. 1993. [70]P. C. Mathur, J. D. Arora, R. P. Sharma, and P. Saxena, “Dependence of Minority Carrier Diffusion Length on Illumination Level and Temperature in Single Crystal and Polycrystalline Si Solar Cells,” J. Appl. Phys., vol. 52, no. 11, pp. 6949–6953, Nov. 1981. [71]H. W. Lu and J. G. Hwu, “Lateral Nonuniformity of the Tunneling Current of Al/SiO2/p-Si Capacitor in Inversion Region due to Edge Fringing Field Effect,” ECS Trans., vol. 58, no. 7, pp. 339–344, 2013. [72]Y. C. Liao, “Investigation of the Deep Depletion Behavior and Oxide Charge Non-Uniformity Effect in MOS(p) and MOS(n) Devices with Ultra-Thin Oxides,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 2013. [73]A. Richter, S. W Glunz, F. Werner, J. Schmidt, and A. Cuevas, “Improved Quantitative Description of Auger Recombination in Crystalline Silicon,” Phys. Rev. B, vol. 86, no. 16, pp. 165202-1–165202-14, Oct. 2012. [74]J. G. Simmons, "Generalized formula for the electric tunneling effect between similar electrodes separated by a thin insulating film," J. Appl. Phys, vol. 34, no. 6, pp. 1793–1803, June 1963. [75]M. Miyamoto, H. Ohta, Y. Kumagai, Y. Sonobe, K. Ishibashi, and Y. Tainaka, “Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics,” IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 440–443, Mar. 2004. [76]Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, L. P. Huang, T. Y. Huang, M. J. Chen, C. H. Diaz, “Modeling Mechanical Stress Effect on Dopant Diffusion in Scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 30–38, Jan. 2005.
|