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研究生:余建朋
論文名稱:單晶片測試機之前端驅動電路設計
指導教授:蘇朝琴
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2001
畢業學年度:89
語文別:英文
中文關鍵詞:測試機前端驅動電路數位纇比轉換器比較器有限狀態機器
外文關鍵詞:testerPE circuitDACcomparatorFSM
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傳統上測試機的前端驅動(PE)電路是將多個元件如參考電壓IC,驅動接收IC等組在一塊板子上。元件間由匯流排傳輸,因而限制住它的速度且面積大。在這個論文中,我們以CMOS待測物為目標來實現PE電路。我們使用tri-stae驅動器與寄生電感來達到規格的速度要求。我們使用兩個不同工作電壓區間的比較器來實現接收器。在電流負載裡我們用電流式數位類比轉換器來取代橋式二極體架構。最後,以TSMC 0.35μm 1P4M CMOS製程來實現我們設計的電路,並用Pre and post simulation 驗證設計的可能性。

Contents
Chapter 1 Introduction……………………………….……………...1
1.1 Motivations……………………………………………………………………..1
1.2 Pin Electronic Survey…………………………………………………………...4
1.3 Thesis Organization……………………………………………………………9
Chapter 2 Architesture of Pin Electronic card Circuit…………….10
2.1 Architecture Overview………………………………………………………...10
2.2 Driver…………………………………………………………………………..10
2.3 Dual Comparator………………………………………………………………13
2.4 Dynamic Load………………………………………………………………….16
2.5 Digital to Analog Converter (DAC)……………………………………………18
2.6 FSM…………………………………………….………………………………21
2.7 Sample and Hold………………………………………………………………..23
Chapter 3 Spec Requirement and Simulation Result………………25
3.1 Spec Requirement………………………….…………………………………...25
3.2 Driver………………..…………………………………………………………26
3.3 Comparator……………………………………………………………………..27
3.4 Load…………………………………………………………………………….30
3.5 DAC and S/H…………..……………………………………………………….32
3.6 Summary………………………………………………………………………..34
Chapter 4 Chip Implement…………….…………………………….35
4.1 Design Flow…………………………….………………………………………35
4.2 Chip implement…………..…………………... ………………….…………….37
4.3 Test result……………………………………………………………………….41
Chapter 5 Conclusion………………………………………..……….44
Reference………………………………………..……….…………...45

[1]King, P.N." Flexible, high-performance pin electronics implementation, "Test Conference, 1989. Proceedings. Meeting the Tests of Time., International , 1989.
[2]Baril, B.; Clayson, D.; McCracken, D.; Taylor, S. “ HIGH PERFORMANCE PIN ELECTRONICS EMPLOYING IC AND HYBRID CIRCUIT PACKAGING TECHNOLOGY, “ Test Conference, 1991, Proceedings., International , Oct. 26-30 1991.
[3]Taylor, S.S. “A high-performance GaAs pin electronics circuit for automatic test equipment, “ Solid-State Circuits, IEEE Journal of , Volume: 28 Issue: 10 , Oct. 1993.
[4]Taylor, S.S.; Nguyen, C.; Davenport, W. “A high-performance GaAs pin electronics chip for high-speed general purpose ATE, “Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1991. Technical Digest 1991., 13th Annual , 1991.
[5]Branson, C. “A high performance, 10-volt integrated pin electronics driver, “Test Conference, 1989. Proceedings. Meeting the Tests of Time., International , 1989.
[6]Branson, C.W. “Integrating tester pin electronics, “ IEEE Design & Test of Computers , Volume: 7 Issue: 2 , April 1990.
[7]Yungseon Eo; Eisenstadt, W.R.; Ju Young Jeong; Oh-Kyong Kwon, “New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design, “Advanced Packaging, IEEE Transactions on [see also Components, Packaging and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on] , Volume: 23 Issue: 2 , May 2000.
[8]Wei-Shang Chu; Current, K.W. “A rail-to-rail input-range CMOS voltage comparator, “Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on , Volume: 1 , 1998.
[9]Mandal, P.; Visvanathan, V. “ Macromodeling of the AC characteristics of CMOS op-amps, “Computer-Aided Design, 1993. ICCAD-93. Digest of Technical Papers., 1993 IEEE/ACM International Conference on , 1993.
[10]Senthinathan, R.; Prince, J.L. “Application specific CMOS output driver circuit design techniques to reduce simultaneous switching noise, “Solid-State Circuits, IEEE Journal of , Volume: 28 Issue: 12 , Dec. 1993.
[11]Liang Dai; Harjani, R. “CMOS switched-op-amp-based sample-and-hold circuit, “Solid-State Circuits, IEEE Journal of , Volume: 35 Issue: 1 , Jan. 2000.
[12]Palumbo, G.; Pennisi, S. “A class AB CMOS current mirror with low-voltage capability, “Electronics, Circuits and Systems, 1999. Proceedings of ICECS '99. The 6th IEEE International Conference on , Volume: 2 , 1999.

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