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研究生:童偉程
研究生(外文):Wei-Cheng Tung
論文名稱:具輸出級誤差消除機制之三位階三角積分D類放大器設計
論文名稱(外文):Design of a Tri-Level Sigma-Delta Class-D Amplifier with Output-Stage Error Cancellation Scheme
指導教授:蔡佩芸蘇純賢
指導教授(外文):Pei-Yun TsaiChun-Hsien Su
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:2008
畢業學年度:97
語文別:中文
論文頁數:70
中文關鍵詞:誤差校正脈衝邊緣延遲雙向鋸齒波D類放大器三角積分
外文關鍵詞:PEDECBSECSigma-Deltaclass-D
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本論文提出一種具輸出級誤差消除機制之三位階三角積分D類放大器設計。D類音頻放大器較傳統的AB類放大器具有高效能的優勢,然而音訊品質上, D類放大器輸出級開關採用脈衝寬度訊號控制,容易造成非線性時序誤差,使得輸出訊號的訊噪比降低。在降低非線性時序誤差方面,類比閉迴路式的脈衝邊緣延遲誤差校正(PEDEC)與雙向鋸齒波誤差校正(BSEC)為常見方式,主要原理是檢測輸出訊號誤差並回授去控制輸入訊號寬度。然此類方法電路中的低通濾波器及類比積分器的電阻與電容過大,造成電路積體化的困難,而使實現成本大幅增加。本論文以類比式脈衝誤差校正理論為基礎,提出一全數位化之誤差補償架構,使得整體D類放大器積體化可以達成並且大幅降低實現成本。此外,本論文將所提架構以三位階三角積分調變技術實現,使得輸出訊號品質更加提升。由模擬顯示,使用傳統類比誤差校正機制可將訊號總諧波(THD)自-30dB至-50dB區間壓抑至-50dB至-75dB左右。而使用本論文將所提架構可將訊號總諧波自-40dB至-70dB區間壓抑至-70dB至-90dB左右,最佳狀況更可至-100dB以下。以硬體實現成本而言,本論文所提架構較之傳統類比式架構電路面積可節省一半以上,並且無晶片外接元件。本論文所提架構在效能與成本上均具備優勢。
A tri-level sigma-delta class-D audio amplifier with output-stage error cancellation scheme is proposed in this thesis. The Class-D topology is superior to Class-AB one for its higher efficiency, however, nonlinear timing error on the output stage caused by the use of pulse-width modulation usually deteriorates output waveform quality. Conventional approaches proposed to solve the timing error problem are so called Pulse Edge Delay Error Cancellation (PEDEC) and Bi-directional Saw-tooth Error Cancellation (BSEC). Both approaches using output feedback to control the shape of input signal pulse. However, such analog correction methods need analog low pass filtering and integration functions with large resistor and capacitor values, preventing system being realized by integrated circuits. This thesis proposed an all-digital error cancellation scheme to overcome the aforementioned problems. By using tri-level sigma-delta modulation techniques, the performance of the proposed architecture can be further enhanced. Simulation results show that the total-harmonic-distortions of the proposed architecture can be suppressed from the range of -40dB and -70dB to -70dB and -90dB, compared to conventional analog approaches which are from the range of -30dB and -50dB to -50dB and -75dB. Furthermore, the circuit area of the proposed architecture is half of the analog approach, and without off-chip components.
第1章 簡介 1
1-1 功率放大器 2
1-1-1 Class A 2
1-1-2 Class B 3
1-1-3 Class AB 3
1-1-4 Class D 4
1-2 研究動機 5
1-3 論文組織 7
第2章 D類放大器工作原理介紹 8
2-1 脈衝寬度調變(PWM) 8
2-2 三角積分調變(SDM) 11
2-2-1 量化誤差(Quantization Error) 11
2-2-2 超取樣(Oversampling) 14
2-2-3 Σ-Δ調變器發展 15
2-3 Class D輸出級架構 26
第3章 D類放大器誤差校正架構設計 28
3-1 脈衝邊界延遲誤差校正(PEDEC) 28
3-1-1 PEDEC-基本原理 28
3-1-2 PEDEC-校正說明 31
3-1-3 PEDEC-限制條件 33
3-2 雙向鋸齒波誤差校正(BSEC) 34
3-2-1 BSEC-校正說明 34
3-2-2 BSEC、PEDEC分析比較 37
3-3 新的數位式誤差校正架構設計 39
第4章 新的數位式誤差校正架構之應用 44
4-1 1-bit & 1.5-bit Class D輸出級 44
4-1-1 1-bit輸出級 44
4-1-2 1.5-bit輸出級 45
4-2 1.5-bit數位式誤差校正架構設計 51
4-2-1 初步構思 51
4-3 1.5-bit數位式誤差校正架構 53
4-3-1 模擬結果 56
4-3-2 量化誤差 60
4-3-3 量化誤差的影響 61
第5章 結論 66
References 67
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