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研究生:鄭英宗
研究生(外文):Ying-Tsung Cheng
論文名稱:透過乾式蝕刻製作新型鍺全包覆式閘極電晶體元件
論文名稱(外文):Dry etching process for Ge Gate-All-Around FETs on Si manufacturing
指導教授:李雄李雄引用關係
學位類別:碩士
校院名稱:國立中央大學
系所名稱:機械工程研究所碩士在職專班
學門:工程學門
學類:機械工程學類
論文種類:學術論文
論文出版年:2012
畢業學年度:100
語文別:中文
論文頁數:87
中文關鍵詞:乾式蝕刻全包覆式元件環繞式閘極電晶體
外文關鍵詞:GeSiGate-All-AroundGAADry etching
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電漿技術在半導體製程中廣泛被應用,例如乾式蝕刻(dry etching)、薄膜沈積、去光阻等等都與電漿技術相關。隨著半導體工業的技術的進步積體電路的尺寸越做越小,所以蝕刻製程是否能精準完成微影中預定圖案轉移,為一個重要的製程。本論文中先在 TEL DRM機台內使用八氟環丁烷(C4F8)、三氟甲烷(CHF3) 、氯氣(Cl2) and溴化氫(HBr)等氣體來進行氧化矽與鍺金屬電漿蝕刻,研究其蝕刻率、均勻度與電漿蝕刻設備參數的關係。
再利用這些機台製程參數來開發出一種新型鍺全包覆式閘極電晶體元件(Ge Gate-All-Around FETs),並藉由蝕刻技術來達到消除界面失配差排(Misfit dislocations),或結合反覆式退火(Cyclic thermal annealing),進ㄧ步降低線差排 ( Threading dislocations ),使之達到高品質鍺懸浮單晶結構,根據此結構可製作具有極佳閘門(Gate)控制和電性表現的新型鍺全包覆式立體結構閘極電晶體。
A novel process to etch away the dislocated Ge near Ge/Si interface from blanket Ge grown on SOI can solve the loading effect in the selective growth, achieve better gate control by gate all around with larger effective width (Weff) as compared to rectangular fin, and have good isolation due to nothing between Ge channel and SOI as well as the valence band discontinuity to keep holes away from Si at source and drain. By dislocation removal, the defect-free Ge channel can be formed on nothing. The device process is also expectedly applicable for bulk FinFET on nothing with similar performance.
第一章 序論..................................................................................................1
1-1 前言....................................................................................1
1-2 論文架構介紹....................................................................4
1-3 研究動機與目的................................................................5
1-4 環繞式閘極電晶體回顧...................................................6
1-5 短通道效應(Short Channel Effects)說明.........................8
1-6 文獻回顧 (Paper Review)................................................9

第二章 電漿蝕刻機制與應用....................................................................18
2-1 電漿簡介.........................................................................18
2-1-1 電漿的產生.....................................................................18
2-1-2 電漿蝕刻機制.................................................................21
2-2 電容耦合式電漿源........................................................23
2-3 高密度電漿源................................................................25
2-3-1 感應耦合型電漿源(ICP)..............................................25
2-3-2 電子迴旋共振電漿源(ECR)........................................27
2-4 乾蝕刻環境的影響......................................................28
2-4-1 蝕刻時反應室腔體壓力的影響...................................28
2-4-2 電漿功率(RF power)的影響........................................29
2-4-3 蝕刻氣體流量的影響...................................................29

第三章 實驗裝置與量測系統....................................................................30
3-1 蝕刻電漿系統...............................................................30
3-2 蝕刻率(Etching rate)量測............................................32
3-3 蝕刻後試片之顯微觀察分析.......................................35
3-4 元件電性量測分析.......................................................36

第四章 實驗裝置與量測系統....................................................................37
4-1 電漿功率對於蝕刻率及均勻度的關係.....................38
4-1-1 氧化矽層中晶圓各點位之蝕刻率關係......................38
4-1-2 鍺金屬層中晶圓各點位之蝕刻率關係......................39
4-1-3 氧化矽層中電漿功率與蝕刻率及均勻度之關係......39
4-1-4 鍺金屬層中電漿功率與蝕刻率及均勻度之關係......40
4-2 腔體壓力與蝕刻率及均勻度的關係..........................40
4-2-1 在不同壓力下,氧化矽層中晶圓各點位之蝕刻率關係..................................................................................41
4-2-2 在不同壓力下,鍺金屬層中晶圓各點位之蝕刻率關係..................................................................................41
4-2-3 氧化矽層中腔體壓力與蝕刻率及均勻度之關係......42
4-2-4 鍺金屬層中腔體壓力與蝕刻率及均勻度之關係......42
4-3 溫度與蝕刻率及均勻度的關係..................................43
4-3-1 在不同溫度下,氧化矽層中晶圓各點位之蝕刻率關係..................................................................................43
4-3-2 在不同溫度下,鍺金屬層中晶圓各點位之蝕刻率關係..................................................................................44
4-3-3 氧化矽層中溫度與蝕刻率及均勻度之關係..............44
4-3-4 鍺金屬層中溫度與蝕刻率及均勻度之關係..............45
4-4 新型鍺全包覆式閘極電晶體元件之製作..................45
4-4-1 新型Ge GAAFET電晶體之製作流程.........................46
4-4-2 Cl2、HBr氣體之電漿蝕刻機制....................................51
4-4-3 N-channel Ge GAAFET製作.......................................54
4-5 新型Ge GAAFET之電性分析與比較.........................55
4-5-1 Drain Current(Id)–Gate Voltage(Vg)特性曲線............55
4-5-2 Drain Current(Id) - Drain Voltage(Vd)特性曲線...........58
4-5-3 Ge GAA p-FET and n-FET驅動電流Ion比較...............60
4-5-4 Ge n- and p- FinFET 之電性比較................................60
4-6 結論................................................................................61

第五章 總結與未來展望.........................................................................64
參考文獻........................................................................................................65
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