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研究生:陳耿男
研究生(外文):Gan-Nan Chen
論文名稱:匯流排上的時間延遲及交談失真的偵錯設計技巧
論文名稱(外文):A Design for Diagnosis technique for the Delay and Crosstalk Measurement of On-chip Bus
指導教授:蘇朝琴
指導教授(外文):ChauChin Su
學位類別:碩士
校院名稱:國立中央大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文出版年:2000
畢業學年度:88
語文別:英文
論文頁數:67
中文關鍵詞:交談失真匯流排時基異變可偵錯設計技巧時間延遲
外文關鍵詞:crosstalkbusjitterdesign for diagnosisdelay
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篇論文主要是對晶片上匯流排提出的可偵錯技術(Design for Diagnosis-DFD)。這個技術重要的特點之一就是使用數位的方法來對晶片上匯流排作時間延遲及交談失真的測試和偵錯。數位時間延遲量測模組(Digital Delay Measurement Module-DMM)可用來處理時間延遲的量測。它計數相位偵測器輸出的工作週期(Duty Cycle)來決定時間的延遲。這工作周期是測試信號和延遲信號互斥。至於偵錯組態可用來決定是匯流排上的驅動器、接收器、或是連接線線發生錯誤。交談失真雜訊的量測可用來對此種現象作進一步的分析。最後,設計一顆全客戶製作(Full custom design)的晶片來對上述的各種功能作驗証及模擬。

This paper is about a design for diagnosis (DFD) technique for the on-chip bus wires. It uses digital method to measure the delay and crosstalk for the testing and diagnosis of on-chip bus wires. For the delay measurement, the digital delay measurement module (DMM) counts the duty cy-cle of the phase detector (PD) output, which is the exclusive-or of the test signal and the delayed sig-nal, to determine the delay. The diagnosis con-figuration can use to identity whether the drivers, receivers, or wires are in fault. The crosstalk noise measurement can be used to analysis the phenomenon. Finally, a full custom chip design is implemented to verify and simulate the above functions.

CHAPTER 1 INTRODUCTION1
1.1 TECHNOLOGY BACKGROUND1
1.2 MOTIVATION2
1.3 OBJECTIVE3
1.4 THE BUS ARCHITECTURE AND MODELING3
1.5 THESIS ORGANIZATION4
CHAPTER 2 DIGITAL DELAY MEASUREMENT6
2.1 THE ANALOG PHASE MEASUREMENT6
2.2 THE DIGITAL DELAY MEASUREMENT MODULE - DMM7
2.3 THE DIGITAL DELAY MEASUREMENT MODULE CONFIGURATION7
CHAPTER 3 THE DELAYDFD ARCHITECTURE11
3.1 THE DELAYDFD ARCHITECTURE11
3.2 THE DELAY MEASUREMENT CONFIGURATION12
3.3 BUS DELAY FAULT DIAGNOSIS14
CHAPTER 4 THE CROSSTALK NOISE18
4.1 INTRODUCTION18
4.2 THE ORIGIN OF CROSSTALK NOISE19
4.3 CROSSTALK NOISE EFFECTS21
4.4 CROSSTALK NOISE AND TIMING JITTER23
4.5 PREVIOUS WORK ABOUT CROSSTALK NOISE24
4.6 CROSSTALK NOISE DFD ARCHITECTURE26
4.7 HSPICE SIMULATION28
4.7.1 CASE 1: THE VICTIM LINE IS KEPT SILENT29
4.7.2 CASE 2: THE VICTIM LINE HAS SIGNAL RUNNING29
CHAPTER 5 FPGA IMPLEMENTATION AND VERIFICATION32
5.1 THE ENVIRONMENT SETUP32
5.2 THE EXPERIMENTAL RESULTS33
5.3 COMPARISON BETWEEN THEORETICAL AND MEASUREMENT VALUE35
5.4 CONCLUSION35
CHAPTER 6 FULL CUSTOM IC IMPLEMENTATION36
6.1 THE TEST CHIP ARCHITECTURE36
6.2 WHAT THE TEST CHIP CAN VERIFY38
6.2.1 CROSSTALK NOISE MEASUREMENT39
6.2.2 DIGITAL DELAY MEASUREMENT41
6.2.3 DESIGN FOR DIAGNOSIS41
6.2.4 EXTERNAL DELAY MEASUREMENT42
6.3 THE CIRCUITS DESIGN44
6.3.1 THE VOLTAGE CONTROLLED OSCILLATOR (VCO)44
6.3.2 THE FREQUENCY DIVIDER45
6.3.3 THE LIMITED SWING DRIVER-RECEIVER PAIR45
6.3.4 THE SCHMITT TRIGGER46
6.3.4.1 The Behavior Manner Analysis47
6.3.4.2 The HSPICE Simulation48
6.3.5 THE LIMITED SWING DRIVER DESIGN49
6.3.5.1 The Multi-Function Driver Configuration50
6.3.5.2 The HSPICE Simulation51
6.3.6 THE LIMITED SWING RECEIVER DESIGN54
6.3.6.1 The Receiver Configuration54
6.3.6.2 The HSPICE Simulation55
6.4 THE TEST CHIP CONTROL CIRCUIT56
6.5 THE TEST CHIP LAYOUT57
6.6 THE TESTING CONSIDERATION58
CHAPTER 7 CELL-BASED DESIGN IMPLEMENTATION59
7.1 INTRODUCTION59
7.2 THE BASIC ARCHITECTURE59
7.2.1 THE TIMING GENERATION MODULE59
7.2.2 THE BUS WIRES LAYOUT60
7.2.3 THE MULTI-DRIVING DRIVER61
7.3 THE TEST CHIP SYNTHESIS61
7.4 THE TEST CHIP LAYOUT62
CHAPTER 8 CONCLUSIONS64
REFERENCE66

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