臺灣博碩士論文加值系統

本論文提出了可配置極化碼(Polar Code)逐次干擾抵銷(Successive Cancellation)解碼器超大型積體電路(VLSI)設計與實作，在硬體架構上以降低面積為目標。在新架構上利用降低硬體平行度方法減少運算元的數量，以達到用時間換取空間的效果，利用架構的特性，讓解碼器可以應對不同的碼長與碼率。本論文使用C與Matlab做為軟體的模擬環境，硬體驗證平台為Xilinx Zedboard 以及Virtex7 FPGA 開發板，積體電路設計使用TSMC 90nm CMOS製程技術進行實作。
論文內容包含極化碼介紹、連續刪除演算法、演算法模擬驗證、解碼器硬體架構、模擬結果及驗證，最後會介紹積體電路設計的流程及其中的參數。

This thesis presents the design and implementation of configurable successive cancellation (SC) polar decoder. Our goal of design is reducing the chip area and it can be implemented by VLSI. The decoder architecture reduces the number of processing units by reducing the hardware parallelism. By using the characteristic of this architecture, the decoder can match with different code length and code rate. This paper uses C and Matlab as the software simulation environment, and the hardware verification platform is Xilnix Zedboard and Virtex7 Board. The decoder is implemented using the TSMC 90nm CMOS technology.
This paper describes the introduction of polar code, successive cancellation decode algorithm, hardware architecture of decoder, simulation result and verification. The implement of VLSI will be introduced in the end of paper as a conclusion.

圖目錄 v
表目錄 viii
第1章 緒論 1
1.1 研究背景 1
1.2 文獻回顧 2
1.3 研究目標 2
1.4 論文架構 3
第2章 極化碼 4
2.1 極化碼介紹 4
2.1.1 基本概念介紹 4
2.1.2 記號說明 5
2.1.3 通道極化 5
2.1.3.1 通道組合 6
2.1.3.2 通道分裂 9
2.1.4 通道極化判定 11
2.2 極化碼 編碼方式介紹 15
2.3 Successive Cancellation 解碼方式介紹 16
第3章 演算法程式模擬與驗證 24
3.1 環境設定 24
3.2 程式解碼流程 29
3.2.1 Initial unit 30
3.2.2 Control unit 30
3.2.3 Decode unit 31
3.3 模擬效能 32
第4章 解碼器硬體架構 36
4.1 傳統硬體方塊圖 36
4.1.1 Main frame 37
4.1.1.1 g function PE 38
4.1.1.2 f function PE 39
4.1.1.3 Merged PE 40
4.1.2 Feedback unit 40
4.2 新型解碼器架構 42
4.3 FPGA模擬環境 44
4.4 FPGA解碼器效能模擬 45
第5章 晶片設計流程與參數選擇 47
5.1 晶片設計流程 47
5.2 記憶體的選擇 48
5.3 I/O Pad的選擇 50
5.4 硬體效能與文獻比較 53
第6章 結論與未來展望 55
參考文獻 56

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