臺灣博碩士論文加值系統

　　網路已經成為人們日常生活中不可或缺的一環，藉著它人們可以互相傳遞私密訊息。為了確保被傳送訊息的安全性、完整性與認證傳送者之身份，資料加密與認證方法已經成為網路技術中一個相當重要的議題。為此， AES-CCM加解密演算法被提出並成為此種標準之ㄧ。本論文根據AES-CCM演算法提出一個高速、高吞吐量之硬體設計架構，並以加密安全程度為考量，完成三種不同版本之AES-CCM演算法之設計與硬體實現，其金鑰長度可以為128位元、192位元及256位元。
　　對於AES-CCM整體架構，我們平行化處理資料驗證與加密訊息兩個部分，並利用資源共享有效地節省硬體資源。為提高性能，在架構中採用雙AES模組。在AES演算法的實現中，使用伽羅瓦複合場運算以降低複雜度；在混合行步驟中，簡化矩陣公式以整合部分運算，達到減少邏輯運算的資源；在金鑰擴展功能使用混合模式的設計，以大幅地縮減資料處理時間，有效地提高整體設計之吞吐量。此外，我們詳細分析了管線化對於AES-CCM演算法中之反饋模式的加密特性之影響，提出了三種版本的設計：替換盒查表實現設計、邏輯運算取代替換盒設計及管線化邏輯運算取代替換盒設計。
　　完成之設計使用Xilinx Virtex7之xc7vx330t-3ffg1157元件實現與驗證。三種設計使用之LUT資源數量分別為48,460個、9,604個及8,871個，工作頻率為168 MHz、66 MHz及279 MHz，吞吐量為196 Mbps、134 Mbps及1,429 Mbps。最後，我們將效能最佳的第三版本以TSMC 0.18製程的ASIC實現與驗證，其工作頻率為83.3 MHz，晶片核心面積為1,249.26 μm × 1,248.96 μm，資料處理最高吞吐量為427 Mbps，消耗功率為35.3 mW。

　Networking has become an indispensable part of the daily life of people. With it, people can communicate with each other by sending private messages. To ensure confidentiality and intactness of the message and authenticate the sender, the message encryption and authentication method has become a crucial issue in networking technique. To facilitate this, the AES-CCM algorithm has been proposed and becomes one of such kinds of standards. In this thesis, we propose a high-speed, high-throughput hardware architecture for the AES-CCM authenticated encrypted algorithm. To improve the degree of encryption security, three different architectures are designed and implemented for the algorithm based on the improving performance. In all these designs, the length of secret keys can be 128 bits, 192 bits, or 256 bits.
　For the overall AES-CCM architecture, we parallelize both data verification and encryption parts and use the concept of resource sharing to effectively reduce hardware resources. To improve the performance, a dual AES architecture is used in the design. In AES algorithm realization, we adopt the Galois composite field to reduce the complexity of operation. In the Mix-Columns step, we simplify matrix formulae to integrate some operations and reduce the resources of logical operations. For the secret-key expansion, a mixed mode design is employed to greatly decrease the data processing time and effectively improve the throughput of the algorithm. In addition, we analyze the impact of pipeline on the feedback mode inherent in the AES-CCM algorithm in detail and propose three architectures: realization of the S-Box as a look up table, realization of the S-Box with unpipelined combinational logic, and implementation of the S-Box with pipelined combinational logic.
　The proposed three designs of the AES-CCM algorithm are verified with the Xilinx Virtex7 xc7vx330t-3ffg1157 device. The number of LUTs used are 48,460, 9,604, and 8,650 respectively. They can separately operate at frequencies of 168 MHz, 66 MHz, and 283 MHz and yield the max throughputs of 196 Mbps, 134 Mbps, and 1464 Mbps, respectively. The design with the best performance is implemented as an ASIC with the TSMC 0.18μm process. The resulting ASIC can operate at 83.3 MHz and achieve a high throughput of 427 Mbps. The core area of the chip is 1,249.26 μm × 1,248.96 μm. The power consumption of the chip is 35.3 mW.

第一章 緒論
1.1 研究動機
1.2 文獻回顧
1.3 研究方向
1.4 章節介紹
第二章 AES-CCM加解密演算法介紹
2.1 密碼學名詞說明
2.2 AES-CCM安全協議與演進
2.3 區塊密碼操作模式
2.4 消息身分驗證種類
2.5 相關數學知識背景
2.5.1 伽羅瓦有現場
2.5.2 加法運算
2.5.3 乘法運算
2.6 AES-CCM演算法
2.6.1 格式化功能模組
2.6.2 AES-CCM加密過程
2.6.3 AES-CCM解密過程
2.7 AES加密標準演算法
2.7.1 金鑰擴展
2.7.2 AES加密過程
2.7.3 AES解密過程
第三章 設計分析與考量
3.1 資料流管線化分析
3.1.1 循環展開
3.1.2 外部回合管線化
3.1.3 內部回合管線化
3.1.4 資源共享
3.2 演算法運算單元分析
3.2.1 替換位元組(SubBytes)運算單元
3.2.2 金鑰擴展功能分析
3.3 資料運算平行化分析
3.3.1 回合運算
3.3.2 雙AES設計
第四章 AES-CCM硬體架構分析與設計
4.1 整體架構
4.2 主控制單元
4.3 格式化模組
4.4 雙AES模組
第五章 FPGA與ASIC設計實現與結果分析
5.1 FPGA設計與實現
5.1.1 模擬時序示意圖
5.1.2 FPGA模擬測試
5.1.3 FPGA結果與效能比較
5.2 標準元件庫設計與實現
5.2.1 RTL階段
5.2.2 邏輯合成階段
5.2.3 晶片佈局階段
5.2.4 晶片結果
5.2.5 晶片效能分析
第六章 結論與未來展望
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