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Protocol processing may be a bottleneck for implementing a high
speed communication. In B-ISDN environment, the input data must
be fast processed to take advantage of the underlying huge
transmission bandwidth. Thus, there are impossible to use the
software for the processing - all processing must be done in
hardware. With the help from the hardware speed, more CPU pro-
cessing can be saved to support other control & OAMP functions.
Therefore, designing peripheral ASICs for promoting high speed
network interface is necessary. In this thesis, we have
presented the hardware architecture of the SAR-T, SAR-R, and
Timer Manager for the ASIC design. Fur- thermore, we select the
SAR-T to simulate the detailed hardware circuit under the
CADENCE tool environment. The Segmentation_Circuit packet which
can provide the maxi- mum output rate up to 160 Mbps is
designed for the SAR Sublayer of the AAL Type 3/4. This circuit
can be used in the design of high speed communication interface
for computer, workstations, bridges, routers, etc. In order to
simplify the design comple- xity, we select PAL device as the
controller for the SAR-T. Most importantly, we adopt 3-stage
pipeline architecture and 16-bit parallel operation design to
promote the segmentation rate up to 160 Mbps. To match the
16-bit parallel full operation, we have also derived a hardware
circuit for implementing the CRC opera- tion in parallel, which
only requires 10 MHz (100 ns) system clock to support such
operation.
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