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There are two main topics in this thesis, one is the VLSI
implementation for the LPC cepstrum algorithm, and the other is
to present two VLSI architectures for implementing the Bayesian
Network. In the first part, a pipelining architecture for
implementing the 8-stage cepstrum algorithm is proposed. The
circuit performs the cepstrum operation for each frame of the
speech data, and its high speed performance can meet the
requirement of real time speech recognition. The cepstrum chip
is fabricated in 1.2 um double-metal CMOS techinology after the
physical design and circuit verification. According to the
chip testing report by the IMS XL-60 tester, the chip can
normally execute up to 18.3 MHz. On the whole, the chip
contains about 24000 transistors which occupy 227*213 mils2.
The process of Bayesian Network is extremely important and has
been used in a variety of speech processing applications such
as isolated,connected speech recognition, speaker verification,
and identification. A major consideration in evaluating the
performance of a recognizer based on the Bayisian Network is
its computational complexity.In the second part, we present two
floating-point architectures for implementing the digital
Bayesian Network,one based on the CORDIC operations and the
other based on the Computing Convergence Method (CCM). The
whole function of Bayesian architecture has been simulated by
the hardware description language (HDL), Verilog, and its data
format is designed to be compatible with IEEE 754 standard.
Therefore, the recognition model, Bayesian Network, can be
implemented into a single chip and applied to the above
applications.
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