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To reduce the load of the share bus in a tightly-coupled
multiprocessor system,write-back cache is often inserted
between each CPU and the share bus.However,the impact on the
share bus load from I/O side is seldom considered. I/O bridge
is referred to a bus bridge between the share bus and the I/O
bus.Its organization is believed to affect the share bus load
imposed by I/O activity.In this thesis,we first survey
possibile I/O bridge organizations.Then,we design an I/O bridge
architecture which can effectively reduce the share bus load
imposed by I/O.In this design, a cache buffer is added to the
bridge and a H/W bus snooping protocol is developed to solve
the data coherence problem.Finally, performance evaluation is
conducted to compare the share bus load impacts of the proposed
bridge design and other possible bridge designs.
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