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Wafer Scale Integration (WSI) has many potential advantages
such as low power consumption, small volume, low system cost,
etc . Nevertheless its feasibility has been investigated for
a long time. In this thesis, we design an electronic Solid-
State Disk ( SSD) which is a practical application of WSI.
Since SSD unlike magnetic disk has no moving mechanical parts
in it,it can provide high data bandwidth and reliable data
access. SSD can fill the latency gap in memory hierarchy
between high speed, high priced main memory and low speed,
low priced hard disk. In order to bypass faulty memory cells
on the wafer, we adapt a loop-based defect-tolerant
interconnection to link memory cells. The interconnection is
bit-serial in order to reduce area overhead and to maintain
reliability. We also propose a parallel testing method which
utilizes built-in verification circuit to test all the cells
in a pipelined fashion. We design the circuit in a top-down
approach. First, we use VHDL ( VHSIC hardware description
language ) to describe its functions, and verify the
description by VHDL simulator. Then Synopsys logic synthesis
tools are used to synthesize our design into gate-level
circuits.
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