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This thesis deals with the design of a low voltage, high speed CMOS programmable frequency counter design. It is the heart of a frequency synthesizer IC because the speed limitation and power consumption of the IC are both depend on the performance of the programmable frequency counter. By using a newly developed end-of-count (EOC) detecting algorithm and a modified ripple down counter, the speed of the new programmable frequency counter is almost three times fast when compared with the conventional one. Because this counter is designed to operate at only 1.35V, consideration about low voltage operation is discussed. A newly designed state- preserving intermittently locked loop (SPILL) technique is introduced, also. This technique can greatly improve the power saving efficient in Time-Division-Multiplexing (TDM) digital radio communication system and wil be widely adapted in the future. From the HSPICE simulation results, the counter can operate at 115MHz with 1.35V power supply voltage, the input signal is only 0.5V peak to peak sine wave and the power dissipation is only 0.5mW. The counter is a 19 bits programmable counter. The programming value N can be 3 to 524287. It can be used to design frequency synthesizer ICs for portable radio communication products such as pager, cordless phone, and portable FM and TV receiver. The portable radio communication products that use these frequency synthseizer ICs can use just one 1.5V battery to replace the heavier 3V or 6V battery and have longer operating time.
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