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At first ,different materials, including low pressure chemical
vapor deposition (LPCVD) TEOS ,LP Si3N4 , plasma enhanced CVD
(PECVD) oxide ,LPCVD borophosphosilicate glass (BPSG) and LPCVD
Poly-Si ,have been systematically fabricated and the spacers
for the VLSI circuits.The electrical properties shows that the
Poly-Si is the best one of all the these spacers due to its
highest dielectric constant ,K=11.9 , This result is consistent
with the literatures.Although Si3N4 has the higher dielectric
constant ,it encounters the stress problems so that it is not
suitable for the practical application. BPSG and PE oxide are
also excluded due to their impurity contents. Hence the
remained two candidates ,TEOS and Poly-Si ,are further
appraised in the second section of this study. The purpose of
the second section is focused on the TEOS and Poly-Si spacers.
By using TEOS and Poly-Si as the spacers with different over
etching (O/E) times ,lightly doped drain (LDD) structures can
be fabricated via the direct implantation of arsenic and boron
ions through these spacers. Then ,this simplified LDD
technology is evaluated to subsitute the conventional LDD
process. Fortunely ,Poly-Si spacers with the O/E times of 50
sec and 60 sec can meet the requirement of hot carrier immunity
comparable to that of the conventional N-MOS LDD devices.
However ,too long O/E time of the Poly-Si spacers results in
the deep penetration of the boron and cause the sub-micron P-
MOS punch through after the high-temperature annealing at 950
C. Consequently ,the sub-micron PMOS with this Poly-Si spacer
will exhibit the normal-on characterics.
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