臺灣博碩士論文加值系統

對於具有完全可測試性之單一有限狀態機的合成研究上已經被廣泛的討論
，然而早期的法則在消除合法／非法相等的序相冗餘故障(valid
/invalid equivalent sequentially redundant fault) 時不是花太多時
間就是需要增加許多面積來完成。在本論文中，我們提出一個有效率的方
法來消除這種故障。同時，我們提出一個合成程序可以合成出具有完全可
測試性的單一有限狀態機。互動有限狀態機(interacting finite state
machines) 可測試性合成上的問題比單一有限狀態機來得複雜且較少被注
意。在互動有限狀態機上仍存在一些問題未被提出。在本論文中，我們考
慮一個串接的有限狀態機而且提出一些有關可測試性方面的問題。我們也
提出一個使非掃描串接有限狀態機得到完全可測試性的合成程序。最後，
我們提出合成單一和串接機器的實驗結果。由實驗結果中可看出我們所提
出的合成程序可以有效率的合成出完全可測試性之單一和串接的序向電路
。

The problems of synthesis for testability of single finite
state machine (FSM) have been extensively studied; however, the
earlier algorithms either take much time or have higher area
overhead to eliminate the valid/invalid equivalent sequentially
redundant faults (SRF's). In this thesis, we present an
efficient procedure to eliminate the valid/invalid equivalent
SRF's in the single FSM. We also outline a synthesis procedureo
synthesize a fully testable non-scan single FSM. The problems
of synthesis for testability of interacting FSM's has received
less attention than single FSM. There still exists some
problems not addressed before. In this thesis, We consider a
cascade machines, and address some problems forestability in
the cascade machines. A synthesis procedure of fully testable
non-scan cascade FSM's is also developed. Finally, we present
experimental results on the synthesis of single and cascade FSM'
s. Experimental results show that our synthesis procedures are
efficient to synthesize both single and cascade fully testable
FSM's.