在此論文中將設計一個2-state, radix-16, 6-level soft-decision ,處
理速度超過 300M bps的維特比 (Viterbi) 解碼器並採用8 微米CMOS技術
來模擬.應用在數位磁性記錄器上的部份響應(partial response) 技術與
最大可能性序列估測器 (Maximum-Likelihood Sequence Estimation)已
證實可大幅提昇記錄密度與記錄可靠性.為了在高速度下執行部份響應通
道的最大可能性序列估測器(PRML) , 在此提出一種進位儲存運算法
(Carry-Save arithmetic)的維特比解碼器, 它結合了平行處理(
parallel processing)與管線架構(pipeline structure) 以達到快速處
理的目的.另外設計一個可串接的模組, 可使解碼速度提昇至所需的要求(
大於 300M bps)

In this thesis, a 2-state, radix-16, six-level soft-decision
Viteri decoder over 300M bps is designed and simulated using
0.8-um double-metal CMOS. Application of partial-response(PR)
signaling and maximum-likelihood sequence detection(MLSD) to
digital magnetic recording had been derived and applied to
increase the storage densities and reliability. To perform
partial-response MLSD at the high data rates, a novel
implementation of the Viterbi detector using carry-save
arithmetic is proposed and allows each word-level and bit-level
operation to be pipelined. A cascadable module is designed to
speed-up the decoding rate to meet the requirement.