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As the speed and complexity of VLSIs continue to improve, power
dissipation is limiting the advance of modern electronic
systems. A method which uses input reordering for the
performance enhancement of CMOS circuits is presented. The
proposed technique achieves significant reduction in power
dissipation of logic gates without extra layout area or
decrease in speed. Input reordering does not change the
functionality, it reorders the positions of inputs to reduce
the propagation delay, switching interval and power
dissipation. Since MOS transistors are not ideal devices,
current will occur before the output nodes of logic gates begin
to change states. Hence if we properly order the input signals
of a gate, the gate will speed up and consume less power
dissipation. The most important advantage of input reordering
is that it is orthogonal to other low power algorithm, and
invariant to the type and technology of circuits.
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