跳到主要內容

臺灣博碩士論文加值系統

(44.201.97.0) 您好!臺灣時間:2024/04/24 12:08
字體大小: 字級放大   字級縮小   預設字形  
回查詢結果 :::

詳目顯示

我願授權國圖
: 
twitterline
研究生:謝建成
研究生(外文):Jang-Chen Hsieh
論文名稱:硼穿透在植入式P+複晶矽閘P型金氧半電晶體引起的特性衰變及其改善技術之研究
論文名稱(外文):Boron Penetration Induced Performance Degradation in P+ Polysilicon Gated P-MOSFET and Its Improvement Technologies
指導教授:方炎坤,蔡能賢
指導教授(外文):Yean-Kuen Fang, Nun-Sian Tsai
學位類別:博士
校院名稱:國立成功大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1994
畢業學年度:82
語文別:中文
論文頁數:160
中文關鍵詞:硼穿透通道穿透閘極引起汲極漏電流
外文關鍵詞:Boron PenetrationChannel Punch throughGate Induced Drain Leakage
相關次數:
  • 被引用被引用:0
  • 點閱點閱:204
  • 評分評分:
  • 下載下載:0
  • 收藏至我的研究室書目清單書目收藏:0
近年來,植入式的 P+ 複晶矽閘結構常用於深次微米的 P-MOS FET 電晶
體。但是硼離子的快速擴散特性往往引起了元件的衰變。本文發現除了起
始電壓的不穩定外, 硼穿透會產生通道穿透提早發生,漏電流增大, 互導
特性圖的失真與閘極氧化層的衰變。本文評估兩種技術改善硼離子的擴散
效應, 一為使用快速加熱流整與再流整降低受熱期間; 二為使用自我對準
矽化鈦製程。本文發現當使用快速加熱製程時, P+ 複晶矽閘 P-型金氧半
電晶體的衰變特性改善不大, 但同時卻產生閘層介面狀態增加。另一方面
當使用矽化鈦製程時, 硼穿透所引起的元件特性衰變可以有效的抑止, 其
結果將有助於次微米工程的發展。
In recent, an implanted P+ polysilicon gated P-MOSFET becomes
more popular in deep submicrometer technology.
Conventionally, the higher diffusivity of boron ion degrades
device performances easily. In our thesis,due to the effect of
boron penetration, new de- vice performancce degradation, such
as punch through of channel, off-state drain leakage,
transconductance instability and gate oxide quality failure,
are found except the previous report of threshold voltage
instability. Also, we compare two types of im- provement
technologies to suppress the effect of boron penetr- ation.
One used rapid thermal flow and reflow for BPSG layers to
reduce the backend thermal cycles, the other used Ti
salicide process. We observed that the rapid thermal annealing
can improve the device performance degradation slightly. But,
interface state is generated by this high thermal stress. In
the meanwhile, the Ti- salicide process can improve these
degradation effectively. This result is helpful in the deep
submicrometer technology of the future.
封面
TABLE CAPTIONS
FIGURE CAPTIONS
Chapter 1 Introduction
1-1 Background
1-2 The Object and Structure of Our Study
Chapter 2 Performance Degradation in P+Poly-silicon Gated P-MOSFET
2-1 New Instabilities of The P+ Polysilicon Gated Device Performance
2-2 BF2 or B Implanted Polysilicon Gate With/Without POCI3 Co-doped
Chapter 3 Suppress Boron Penetration With RTA
3-1 Introduction
3-2 RTA Preventation in Boron Penetration
3-3 The Origin of Device Performance Degradation Caused by RTA
3-4 Improvement of The Device Performance Degradation Caused by RTA
Chapter 4 Supress Boron Penetration With Ti-polycide
4-1 Introduction
4-2 Experiments
4-3 Results and Discussion
Chapter 5 Conclusion
REFERENCES
PUBLICATION LIST
TABLES AND FIGURES
QRCODE
 
 
 
 
 
                                                                                                                                                                                                                                                                                                                                                                                                               
第一頁 上一頁 下一頁 最後一頁 top