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Due to the rapid increase in the density of digital integrated circuit, the number of logic within a single chip has become extremely high. This makes the chips hard to test since there is little access to the internal circuit elements. Many digital Design-For-Testability (DFT) techniques has been developed to reduce the difficulty of test generation by increasing accessibility to internal elements of a circuit. Boundary Scan and BIST gain great popularity among several DFTs. With the integration of analog and digital circuits on a signle device, the testing of mixed-signal circuits is even more difficult than digital circuits. A solution to the testing problem is the development of an Analog Design for Testability that similar to its digital counterpart. In this thesis, two new Analog Boundary Scan architectures employing concepts similar to digital Boundary Scan is proposed to provide structured access to the analog signal in a mixed-signal device. Moreover, a system which automatically inserts test circuits to a circuit described in VHDL is developed. This system consists of two subsystems: Boundary scan automatic insertion and BIST automatic insertion. According to the proposed analog boundary scan architecture and the digital boundary scan standard, the Boundary Scan automatic insertion subsystem can cope with not only digital but also mixed-signal circuits. The basic principle of BIST is to insert extra circuitry so that the generation of test patterns and verification of test results occur within the circuit itself. In our BIST automatic insertion subsystem, such extra circuitry is provided for both digital and analog circuits.
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