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Albus首先提出將小腦神經內訊號處理特性以公式化方式來表示之研究，
此小腦(CMAC)類神經網路模式在求取輸入輸出關係具有極佳效率。CMAC模
式採用區域性加權值調整方式，使其具有快速學習及高收斂率優點,且加
權值存取可設計成查表方式，在硬體實現上，很容易成功。基於上述優越
性，小腦類神經網路模式適合應用於色彩重現處理系統上，並被証明即使
彩色影像掃描器與印表機間存在複雜非線性關係，仍能使彩色影像逼真重
現。為了實現縮小晶片面積及快速運算的硬體架構,有必要發展一個新的
對應加權值儲存單元位址和計算輸出向量的硬體架構。本論文提出可由輸
入量化值直接對應加權值儲存記憶單元位址之演算法，大量減低對記憶體
的需求，提高記憶體使用效率，且不需為減少記憶體的需求而另外設計資
料壓縮電路，並具有可並行存取加權值、快速求取輸出向量等優點，使硬
體製作可靠度大為提高，同時製作成本也大為降低。
Cerebellar Modular Articulation Controller (CMAC) was
proposed by Albus to formulate the processing characteristics
of the cerebellum. This model has the ability of learning
arbitrary nonlinear relationships existing between input and
output data. Unlike the backpropagation-styled neural network,
CMAC is characterized by the feature of local weight updating.
By the feature, it has the advantage of fast learning and
high convergence rate in function approximation problems.
Besides, in the aspect of hardware implementation ,CMAC is
easy to be implemented by the table look-up technique. Due to
the superiority in function approximation, CMAC is suitable
for being embedded in a color image reproduction system. In
such system, to make sure that the printed output images can
faithfully reproduce the original input images, CMAC is used
to overcome the nonlinear mapping problem existing
between image scanning device and image printing device. To
implement the CMAC hardware in a condensed area and with
a fast speed, we need a novel architecture for weight
cell address generation and output vector computation.
This thesis proposes a direct weight cell address
mapping algorithm to generate physical addresses of the
weight cell to be read. By this algorithm, we can
obtain a CMAC architecture with a very high usage
efficiency of weight cell memory. Therefore, the requirement
of memory capacity in implementing the CMAC chip is
sharply reduced and hash-coding may not be necessary.
Besides, the CMAC chip can operate in a very high speed due
to the parallel retrieving of weight cells.
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