本論文中,主要探討的是以切換執行方式設計的多引線處理機,如何在多處
理機系統中利用存取共享記憶體時所發生的長延遲時間,來切換不同的引
線執行,隱藏這段原本在RISC機器中所浪費的時間。由於引線切換主要是
以快取失誤時來觸發,如果不對同步指令善加處理,將會造成管線中的死結
。因此我們設計了一組專門處理多引線架構的指令,並由其衍生出引線切
換的不同狀況。我們設計了一套整合的多處理機模擬系統,並將此多引線
處理機模擬器併入這個整合模擬器中。這套多處理機模擬整合系統,為了
求取較佳的模擬效率,採用平行模擬的方式來設計。我們採用的平行環境
是PVM (Parallel Virtual Machine)。目前我們已在SUN SPARC工作站上
建立好此套多處理機平行模擬及評估環境,並完成初步的測試驗證工作,在
論文中我們並以此套模擬環境來評估我們所設計的多引線處理機效能,所
得之結果可供未來設計時之重要參考。

The issues of this thesis are to design a concurrent multi-
threaded architecture based on multiprocessing environment.
This architecture takes advantage of wasted long shared memory
accessing latency to context-switch to another active threads
to hide this latency by executing another threads. The basic
condition for context-switch is load-miss, however, if the
synchronization instructions are not handled well, there will
be deadlock in the processor pipeline. For this reason we
design a set of thread-related instructions, and according to
these instructions we develop a set of context-switch
conditions. We design an integrated multiprocessing simulation
environment, and link our multi-threaded processor simulator
into this integrated environment. For better efficiency of
simulation, this integrated environment is designed and
implemented in parallel fashion. Our parallel environment and
tools is PVM (Parallel Virtual Machine). Currently we have
implemented this integrated parallel multiprocessing simulation
environment on SUN SPARC workstations, and have finished the
first-step testing and evaluation. In the thesis we use this
simulator to evaluate the performance of our multi-threaded
processor design. These statistics are very useful for future
design and development.