在本篇論文中提出了一個具有同時運算結構的視訊處理器，在這個結構中
有三個獨立的運算單元：算術單元、乘法器單元以及離散餘弦轉換/反離
散餘弦轉換單元，它們都被適當地管線化以達到高產出及高運算同時性的
目標。記憶體部份包括六個晶片內建的雙埠區塊記憶體及一個十六字組的
暫存器集。記憶體大小、位址產生器及匯流排架構都被適切地設計以達高
度的硬體使用率。此外，本視訊處理器採用向量管線結構並支援向量型態
指令、累加型態指令、以累加暨最大最小值偵測型態指令，以提高影像應
用程式的執行效率。所有的運算及貯存單元都能夠同時運作。此具運算同
時性之視訊處理器的功能及時序已用Verilog-XL驗證，其中最大延遲時間
發生在最大的區塊記憶體的讀取時間。當時脈速率為30MHz時，此視訊處
理器的運算能力可達1.59GOPS。

In this thesis, a video signal processor(VSP) with a concurrent
architecture is proposed. This architecture consists of three
independent processing units: the arithmetic unit(AU), the
multiplier unit(MU) and the DCT/IDCT unit(DU). They are
suitably pipelined to pursue high throughput and high
concurrency. Six two-port block memories and a 16-word register
file are built on-chip. The memory size, the address
generators, and the bus structure are also well designed to
achieve higher hardware utilization. Moreover, the VSP
incorporates a vector-pipeline architecture, and the VSP
supports vector-type, accumulation- type and accumulation-with-
MMD-type instructions to increase the execution efficiency in
video applications. All processing units and storage units can
operate concurrently. The function(and timing) of this VSP has
been simulated using Verilog-XL. The critical delay is the
access time of the largest block memory, and if the clock speed
is 30MHz, 1.59GOPS sustained processing power is available.