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In this thesis, a video signal processor(VSP) with a concurrent architecture is proposed. This architecture consists of three independent processing units: the arithmetic unit(AU), the multiplier unit(MU) and the DCT/IDCT unit(DU). They are suitably pipelined to pursue high throughput and high concurrency. Six two-port block memories and a 16-word register file are built on-chip. The memory size, the address generators, and the bus structure are also well designed to achieve higher hardware utilization. Moreover, the VSP incorporates a vector-pipeline architecture, and the VSP supports vector-type, accumulation- type and accumulation-with- MMD-type instructions to increase the execution efficiency in video applications. All processing units and storage units can operate concurrently. The function(and timing) of this VSP has been simulated using Verilog-XL. The critical delay is the access time of the largest block memory, and if the clock speed is 30MHz, 1.59GOPS sustained processing power is available.
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