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This dissertation includes two parts. The first part is the
physical analysis of the CMOS transient latchup in the
parasitic p-n-p-n path of CMOS ICs. The second part is the
application of SCR devices on the ElectroStatic Discharge (ESD)
protection circuits. A new physical criterion and an analytical
timing model for trnasient latchup in a p-n-p-n structure are
developed and verified. With the piecewise-linearized method, a
timing model of transient latchup in terms of device parameters
is derived. Model calculation results using the developed
criterion and timing model agree very well with both SPICE
simulation and experimental results. In order to deeply
characterize the mechanisms of the positive-feedback
regeneration during CMOS latchup transition, a novel method is
developed. The positive-feedback regeneration in a p-n-p-n
structure can be definitely modeled by this positive transient
pole method. Based on the clear understanding on the transient
latchup mechansim in the p-n-p-n structure of CMOS ICs, there
are three robust CMOS on-chip ESD protection circuits with the
lateral SCR devices proposed in this thesis. The first is the
dual-SCR ESD protection circuit which consists of dual
parasitic SCR structures between input and VDD node. The second
is the complementary-SCR ESD protection circuit which consists
of two parasitic lateral SCR devices and two junction diodes
merged together to save more layout area. The third is the four-
SCR ESD protection circuit which consists of four parasitic
lateral SCR devices with low ESD trigger voltages to protect
NMOS and PMOS devices of the internal circuits against the ESD
pulses with both positive and negative polarities to either VDD
or VSS(GND) nodes.
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