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This dissertation presents a systematic approach to design VLSI arrays for the discrete sinusoidal transforms. Considering from the aspects of algorithm, architecture, and implementation, the presented approach adopts the cyclic convolution formulation, systolic array realization, and memory-based implementation. Using the presented approach can yield VLSI array designs which are more efficient in hardware than the conventional systolic arrays based on multipliers and the distributed arithmetic architectures. In addition, in this dissertation, we also develop a new formulation for the multi-dimensional discrete Hartley transform such that we can avoid the undesirable overhead in the hardware designs resulted from the conventional design approach.
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