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研究生:王國華
研究生(外文):Wang, Guo Hua
論文名稱:以函數分解作多階邏輯合成之研究
論文名稱(外文):A study of functional decomposition for multilevel logic synthesis
指導教授:陳正陳正引用關係黃婷婷黃婷婷引用關係
指導教授(外文):Chen, ZhengHuang, Ting Ting
學位類別:博士
校院名稱:國立交通大學
系所名稱:資訊工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1994
畢業學年度:82
語文別:中文
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Cover
Abstract(in Chinese)
Abstrach(in English)
Acknowlegements
Table of Contents
List of Figures
List of Tables
1 INTRODUCTION
1.1 Background
1.2 Motivations
1.3 Organization of This Dissertation
2 LITERATURE SURVEY
2.1 Repressntation of Boolean Functions
2.2 Technology Independent Optimization
2.2.1 Global Optimization Methods
2.2.2 Peephole Optimization Methods
2.3 Technology Mapping
2.3.1 Traditional Methods
2.3.2 Boolean Matching[111-121]
2.3.3 Technology Mapping for FPGA''a[22-35]
2.4 Discussions and Our Approaches
3 TRANSFORMATION TECHNIQUES OF OBDD''S
3.1 Introduction
3.2 Ordered Binary Decision Diagrams
3.3 Permutation Eqyivalence Classes
3.4 transpositional Operator
3.5 transformation Concept of OBDD''s and Its Applications
3.5.1 Transformation Concept
3.5.2 Applications
3.6 Experimental Results
3.7 Conclusions
4 OVERLAPPED EDCOMPOSITIONS
4.1 Introduction
4.2 Communication Complexity Driven Multilevel Logic Synthesis
4.3 Overlapped Decomposition
4.3.1 Problem Description
4.3.2 Design Issues and Our Algorithm
4.3.3 Definitions
4.4 Detecting Globals and Finding Input Partitioning
4.4.1 Gain Function of Overlapped Decompositions
4.4.2 Computing the Communication Complexity for Incompletely Specified Functions
4.4.3 A Heuristic for Detecting Globals and Finding Input Partitioning
4.5 Deriving Subfunctions
4.6 Decomposition Don''t Cares(DDC''s)
4.7 Experimental Results
4.8 Conclusions
5 BOOLEAN MATCHING
5.1 Introduction
5.2 Binary Decision Diagrams and Boolean Matching
5.3 Cofactor and Equivalence Signatures
5.3.1 The Communication Complexity of Boolean Functions
5.3.2 Definitions of the Signatures
5.3.3 Properties of the Signatures
5.4 The Matching Algorithm
5.5 Setting Inputs Constants, Bridging Inputs, and Don''t Cares
5.6 Experimental Results
5.7 Conclusions
6 TECHNOLOGY MAPPING FOR Xilinx-3000 FPGA''s
6.1 Introduction
6.2 Functional Decomposition and FPGA Mapping
6.2.1 Simple and Complex Decompositions
6.2.2 FPGA Mapping with Complex Disjoint Decomposition
6.3 system Overiew
6.4 A Mapping Algorithm for Totally Symmetric Functions
6.4.1 Symmetric Functions
6.4.2 A Weight Based Algorithm
6.4.3 FPGA Technology Mapping
6.5 A General Decomposition Algorithm
6.5.1 Output Partition
6.5.2 Variable Partition
6.5.3 Don''t Care Assignment
6.5.4 Encoding
6.6 Experimental Results
6.7 Conclusions
7CONCLUSIONS AND FUTURE WORKS
7.1 Summary of Our Works
7.2 Future Works
BIBLIOGRAPHY
A ANALYSIS OF Fast-Decompose ALGORITHM
A.1 Upper Bound on the Number of Full-Adders
A.2 Upper Bound on the Number of Levels
Vita
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