臺灣博碩士論文加值系統

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 CoverAbstract(in Chinese)Abstrach(in English)AcknowlegementsTable of ContentsList of FiguresList of Tables1 INTRODUCTION1.1 Background1.2 Motivations1.3 Organization of This Dissertation2 LITERATURE SURVEY2.1 Repressntation of Boolean Functions2.2 Technology Independent Optimization2.2.1 Global Optimization Methods2.2.2 Peephole Optimization Methods2.3 Technology Mapping2.3.1 Traditional Methods2.3.2 Boolean Matching[111-121]2.3.3 Technology Mapping for FPGA''a[22-35]2.4 Discussions and Our Approaches3 TRANSFORMATION TECHNIQUES OF OBDD''S3.1 Introduction3.2 Ordered Binary Decision Diagrams3.3 Permutation Eqyivalence Classes3.4 transpositional Operator3.5 transformation Concept of OBDD''s and Its Applications3.5.1 Transformation Concept3.5.2 Applications3.6 Experimental Results3.7 Conclusions4 OVERLAPPED EDCOMPOSITIONS4.1 Introduction4.2 Communication Complexity Driven Multilevel Logic Synthesis4.3 Overlapped Decomposition4.3.1 Problem Description4.3.2 Design Issues and Our Algorithm4.3.3 Definitions4.4 Detecting Globals and Finding Input Partitioning4.4.1 Gain Function of Overlapped Decompositions4.4.2 Computing the Communication Complexity for Incompletely Specified Functions4.4.3 A Heuristic for Detecting Globals and Finding Input Partitioning4.5 Deriving Subfunctions4.6 Decomposition Don''t Cares(DDC''s)4.7 Experimental Results4.8 Conclusions5 BOOLEAN MATCHING5.1 Introduction5.2 Binary Decision Diagrams and Boolean Matching5.3 Cofactor and Equivalence Signatures5.3.1 The Communication Complexity of Boolean Functions5.3.2 Definitions of the Signatures5.3.3 Properties of the Signatures5.4 The Matching Algorithm5.5 Setting Inputs Constants, Bridging Inputs, and Don''t Cares5.6 Experimental Results5.7 Conclusions6 TECHNOLOGY MAPPING FOR Xilinx-3000 FPGA''s6.1 Introduction6.2 Functional Decomposition and FPGA Mapping6.2.1 Simple and Complex Decompositions6.2.2 FPGA Mapping with Complex Disjoint Decomposition6.3 system Overiew6.4 A Mapping Algorithm for Totally Symmetric Functions6.4.1 Symmetric Functions6.4.2 A Weight Based Algorithm6.4.3 FPGA Technology Mapping6.5 A General Decomposition Algorithm6.5.1 Output Partition6.5.2 Variable Partition6.5.3 Don''t Care Assignment6.5.4 Encoding6.6 Experimental Results6.7 Conclusions7CONCLUSIONS AND FUTURE WORKS7.1 Summary of Our Works7.2 Future WorksBIBLIOGRAPHYA ANALYSIS OF Fast-Decompose ALGORITHMA.1 Upper Bound on the Number of Full-AddersA.2 Upper Bound on the Number of LevelsVitaPublication List
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