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Shared buffer memory switch owns some merits such as higher
bandwidth utilization and less memory capacity. Buffer sharing
can reduce the amount of hardware compared with a separated
output buffer switch. Moreover, modifying the memory control
circuits of the switch makes the memory switch enough to
perform multicasting function. However, multicast cells always
own higher priority to be served in original architecture such
that unicast cells must endure longer delay time. In this
thesis, we propose two methods to overcome this unfair
phenomenon. However, the implementation is simple. The first
method is called the "bandwidth balancing circuit" scheme. The
principle of the scheme is that a new up/down counter is added
in original SBMS circuit for counting the number of multicast
cells which have been sent out already. When the content of the
counter reaches a upper bound, both counters will be reset to
zero and every output port in the switch serves an available
unicast cell at the next cell time. The second method is called
"Multicast-to- Unicast Ratio" (MUR) scheme which replaces the
original multicast circuit with the MUR circuit and replaces
cell register with separated "multiple cell-register queues"
each with the capacity of a few cell space. The service order
for two kinds of cells is decided by a ratio of unicast cell
queue length and multicast queue length in output queue #i of
the cell buffer memory. These schemes may effectively allocate
the output bandwidth for these two kinds of cells.
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