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We present C-testable carry-skip and carry- lookahead adders.
The size of the adders is 4k bits, where k is an arbitrary
positive integer. Test patterns of a 4-bit group can be
generated by analysis or an ATPG. These test patterns can be
expanded to test a 4k-bit adder containing more than one group.
The number of expanded test patterns are shown to be
independent of the size of these adders. The number of test
patterns is 17 for the carry-skip adder and 28 for the carry-
lookahead adder. We also discuss ALU circuit design and
testing. The ALU designs are based on four types of adder: (1)
the ripple carry adder, (2) the Manchester carry chain, (3) the
carry-skip adder, and (4) the carry-lookahead adder. The ALU
based on ripple carry adder needs 48 test patterns under the
single cell fault model. The ALU with Manchester carry chain is
similar to a ripple carry adder. It needs 7 test patterns to
test single stuck-at faults. If we consider the stuck- open or
stuck-on fault in the Manchester carry chain, it needs 61 test
patterns. If the ALU is based on the carry-skip or the carry-
lookahead adder, it needs 16 or 23 test patterns, respectively.
C-testability of these ALUs is verified by fault simulation. We
also present a concurrent error detection (CED) arithmetic unit
for the above ALUs. We use a low cost residue code with the
modulus of 7 to design a TSC checker. Also, we show that the
arithmetic unit with the ripple carry, the carry-skip, and the
carry- lookahead adders are all TSC by mathematic analysis and
fault simulation. The hardware redundancy of the mod-7 checker
are compared with Berger check prediction (BCP) checker, and is
shown to be less than BCP checker.
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