臺灣博碩士論文加值系統

波管式電路的特色在於不必添加多餘的記憶元件，即得以高於組合電路延
遲的時鐘速度運行。此外，其功率－速度積與面積－速度積亦極佳，足以
作為極高速電路之典範。然而，目前之研究僅多止於組合電路之時序方面
之最佳化，或是達成最高速運行之實作或演算法；對於系統設計之流程與
測試相關問題，則甚為匱乏。本研究之目的即在於提供一系統設計之觀念
，以一二階段之設計流程完成波管式電路之邏輯設計，並首先提出一強建
式之波管式電路測試法以針對波管式電路中特有之缺失達成偵測之目的。
此外，本論文亦提出將波管式設計應用於前瞻式電路之方法，以及設計前
瞻式電路之正規方法。本研究之特色如下：在設計流程方面先於第一階段
中完成積木電路之面積與速度之曲線以描述設計中之妥協關係。於此，吾
人提出一演算法以求得不同設計下所需增加的晶片負荷；並以線性規劃方
式除去多冗之電路以得最佳之設計。於第二階段中，吾人針對可能發生之
時序問題予以解決，同時利用位準感應式閂鎖的相位共享特性，重新分配
積木電路之延遲規格，冀達成面積最小化之目的。於電路測試方面，吾人
所提出之波管式錯失模型乃針對此種電路特性之目前唯一模型。吾人將電
路製造中因製程波動而造成之可能偏差納入考量，提出一統計之觀點與機
率式之錯失涵蓋率模型。本研究亦提出一強建式之測試演算法，以確保輸
入之測試圖樣能針對選定之錯失進行偵測，而不受非選定測試路徑上之其
他訊號干擾。

Wave pipelining is a new timing technique to boost pipeline
rate of a system from two to ten times as fast without
additional re- gisters. Current research aims at the
implementation, clock sch- emes, and layout issues. This work
concentrates on the design flow and test of wave faults. The
application is on synchronous CMOS digital systems where
latches are used to form multi-stage pipelines. We handle the
area-time issues of wave pipelined cir- cuits, achieve error-
free design, and two step design flow. The feedback loop
problem is also tackled. On the test part of the work, We
define the wave fault, propose a statistical and proba- bility
fault coverage, and a robust test generation algorithm. As a
by-product of our research, we propose the formalism to de-
sign lookahead circuits. We show that the iterative network
imp- lementation of a FSM can be mapped to a lookahead circuit.

COVER
Contents
Preface
Abstract
1. INTRODUCTION
1.1 Pros and Cons of Wave Pipelining
1.2 Related Research on Wave Pipelining
1.3 Technology Considerations
1.4 Motivation and Overview
2. WAVE PIPELINING DESIGN ISSUES
2.1 INTRODUCTION
2.2 APPROACH OVERVIEW
2.2.1 Target Synchronous CMOS Systems
2.2.2 Proposed Design Approach
2.3 MODELS
2.3.1 CMOS Gate Delay and Assertion Times
2.3.2 Logic Block Delay and Assertion Times
2.3.3 Latch Delay and Assertion Times
2.3.4 Logic Networks
2.3.5 Setup and Hold Time
2.4 DESIGN ALGORITHMA AND STRATEGIES
2.4.1 Equivalent Setup and Hold Time Errors
2.4.2 Area-Time Model Contruction
2.4.3 Timing Constraint Assignment
2.4.4 Phase Sharing Formulation
2.4.5 Feedback Loops Formulation
2.5 EXPERIMENTAL RESULTS
2.6 CONCLUSION
3. WAVE PIPELINED LOOKAHEAD CIRCUITS
3.1 INTRODUCTION
3.2 MATHEMATICAL FOUNDATION
3.2.1 Boolean Vector and Boolean Matrix
3.2.2 Boolean Vector Function and Boolean Matrix Operation
3.2.3 Linear Mapping of Boolean Vector Function
3.3 DESIGN FORMALISM
3.3.1 Iterative Array and Lookahead Matrix
3.3.2 Prefix Problem Formulation
3.3.3 Recurrence Sequence Transformation
3.4 EXAMPLES
3.4.1 Carry Adder
3.4.2 Parity Checker
3.4.3 Comparator
3.5 CONCLUSION
4. TESTING WAVE PIPELINED CIRCUITS
4.1 INTRODUCTION
4.2 DELAY TEST BASIS
4.3 FAUIT MODELS
4.3.1 Wave Fault Model
4.3.2 Statistical Model and Fault Coverage
4.4 WAVE FAULT TEST
4.4.1 Robust Wave Test
4.4.2 Wave Fault Test Generation
4.5 RESULT
4.6 CONCLUSION
5. CONCLUSION
Biography
OTHERS