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研究生:秦旭沅
研究生(外文):Shu-Yuan Chin
論文名稱:高性能資料轉換器及能隙參考源之設計與分析
論文名稱(外文):The Design and Analysis of High-Performance Data Converters and Bandgap References
指導教授:吳重雨
指導教授(外文):Chung-Yu Wu
學位類別:博士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1995
畢業學年度:83
語文別:英文
論文頁數:171
中文關鍵詞:能隙參考源數位類比轉換器類比數位轉換器臨界電壓。
外文關鍵詞:bandgap referenceD/A converterA/D converterthreshold voltage.
相關次數:
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  • 收藏至我的研究室書目清單書目收藏:2
本論文的主要宗旨在於設計及分析高性能的資料轉換器及能隙參考電壓電
流源,這些電路及次系統乃是訊號處理最主要的組成單元。其中類比數位
間的轉換器乃是訊號處理時的介面,而能隙參考源則提供資料轉換器必要
的參考電壓或電流。本論文共設計了四個晶片,都已成功地驗證,其中包
含(1)精準的能隙參考電壓電流源,此乃利用一種全新的二次溫度效應補
償方法來提供二次溫度效應補償。(2)應用於視頻的高速數位類比轉換器
,利用一種新型的電流矩陣,它能克服臨界電壓誤差所產生的線性誤差,
所以能夠以簡單的電路設計,輕易達成高速度及高精準度的數位類比轉換
器。(3)應用於音頻的高精準類比數位轉換器,利用新的切換電容方法,
使轉換器的精準度既與電容的比值無關,也對運算放大器的有限增益不太
敏感。(4)應用於視頻的高速類比數位轉換器,使用兩階段式及平行處理
的架構來設計3V高速類比數位轉換器,以求在很少的類比電路之下達到精
準又快速的要求。我們廣泛地研究音頻及視頻訊號處理所需的資料轉換器
及參考電壓電流源,並提供了一些可行的解決之道。我們相信本論文所提
出的高性能的資料轉換器及能隙參考電壓電流源,在設計類比與數位間的
介面時,能提供相當有用的方法及技術。而這些使用的方法及技術也應該
能使用於更多方面的應用,這些應用值得我們於將來做更深入的研究與探
討。
This thesis describes the design of high-performance data
converters and bandgap references which are the essential com-
ponents of signal processing. The designed components include:
(1) voltage and current references which are used to generate
precise and stable output voltages or currents; (2) a high-
speed digital-to-analog (D/A) converter which is used to
transfer the input digital code to output analog form in the
video domain; (3) a medium-speed algorithmic analog-to-digital
(A/D) converter which is used to encode input analog voltages
into equivalent digital codes in the audio domain; (4) a low-
voltage high-speed A/D converter which is used to convert input
analog voltages into digital codes in the video domain. These
voltage and current references circuits use the difference of
MOS source- gate voltages to perform efficient curvature-
compensation. In the D/A converter, a new current source called
the threshold-voltage compensated current source is used to
reduce the nonlinearity. The design of a CMOS algor- ithmic A/D
converter is insensitive to capacitor-ratio accuracy as well as
finite gain and offset voltage of operational ampli- fiers. In
the design of a 3 V high-speed CMOS A/D converter,two- step
subconverter architecture with 5-bit coarse and 3-bit fine
stages, as well as two subconverters in parallel processing are
used to increase the conversion rate.
COVER
ABSTRACT(CHINESE)
ABSTRACT(ENGLISH)
ACKNOWLEDGMENT
CONTENTS
TABLE CAPTIONS
FIGURE CAPTIONS
CHAPTER 1 INTRODUCTION
1.1 Signal Processing
1.2 CMOS Bandgap Voltage References
1.3 COMS D/A Converters
1.4 COMS A/D cONVERTERS
1.5 Organization of This Thesis
Fig 1.1-1.5
CHAPTER 2 HIGH-PRECISION CURVATURE-COMPENSATED COMS BANDGAP VOLTAGE AND CURRENT REFERENCES
2.1 Introduction
2.2 Circuit Analysis and Operational Principle
2.2.A Band-Gap Voltage References
2.2.B Band-Gap Current References
2.3 Design Strategies and Connection
2.3.A Current-Mirror Connection
2.3.B Device Size Optimization
2.4 SPICE Simulation and Experimental Results
2.4.A SPICE Simulation Results
2.4.B Experimental Results
2.2 Summary
Fig. 2.1-2.11
Table 2.1
CHAPTER 3 HIGH-SPEED D/A CONVERTERS WITH THRESHOLD-VOLTAGE COMPENSATED CRUUENT SOURCES
3.1 Introduction
3.2 Chip Design
3.2.A Two-Stage Architecture
3.2.B Threshold-Voltage Compensated Current Sources
3.2.C Two-Stage Weighted-Current-Source D/A Converter
3.2.D Chip Implementation
3.3 Experimental Results
3.4 Summary
Fig 3.1-3.16
Table 3.1-3.2
CHAPTER 4 RATIO -INEDPENDENT ADN GAIN-INSENSITIVE ALGORITHMIC ANALOG-To-DIGITAL CONVERTERS
4.1 Introduction
4.2 Gain-and Ratio-Insensitive A/D converter
4.2.A General Principle of An Algorithmic A/D Converter
4.2.B The Operation Sequence of the Proposed A/D Converter
4.3 Circuit Implementaion
4.3.A Circuit Implementation
4.3.B Minisization of The Switching Noise
4.4 Accuracy Consideration
4.4.A Effect of Op Amp Gain and Offset
4.4.B Effect of Switch-Induced Error Voltage
4.5 Experimental Results
4.6 Summary
Fig 4.1-4.10
Table 4.1-4.3
CHAPTER 5 3V HIGH-SPEED A/D CONVERTERS WITH PARALLEL PROCESSING CAPABILITY
5.1 Introduction
5.2 Architechure of the Proposed A/D Converter
5.2.A Parallel Processing
5.2.B The Structure of A 8-Bit A/D Converter
5.2.C Digital Error Correction
5.3 Design and Analysis of Complete Circuits
5.3.A Coarse Comparator
5.3.B Fine Comparator
5.3.C Resistor Ladder Based Reference Generator
5.3.D Transient Point detector
5.4 Layout and Experimental Results
5.4.A Layout
5.4.B Experimental Results
5.5 Summary
Fig 5.1-5.13
Table 5.1
CHAPTER 6 CONCLUSION AND FUTURE WORK
6.1 Main Results of This Thesis
6.2 Future Work
REFERENCES
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