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This thesis describes a 2~V 2~GHz phase-locked loop (PLL) which
is composed of a phase frequency detector, charge-pump filter,
variable frequency oscillator (VFO) and a multi-modulus
divider. The phase-frequency detector (PFD) compares the phase
of the two clock inputs. The minimum phase difference that PFD
can detects is 0.3ns. The charge-pump filter converts the
sequential logic states of the PFD''s outputs into analog
signals which is suitable for controlling the VFO. The output
voltage of charge-pump filter is linearly proportion to the
phase error of the two clock inputs. The output frequency range
of the negative resistance LC-tuned oscillator is from 1.19~GHz
to 2.35~GHz. A multi-modulus frequency divider allows a PLL to
achieve fine frequency resolution and fast switching time at
the same time, when the multi-modulus divider is controlled by
a sigma-delta modulation. The maximal input frequency of the
multi-modulus divider is 1.6~GHz at $125~\DegC{}$. The divide
number of the divider is from 64 to 126.The power consumption
of multi-modulus divider is 68~mA.To reduce the phase noise
caused by accumulated delays from the first stage to the last
stage, A resynchronous circuit is designed. The PLL is
fabricated with 1.0~um BiCMOS technology. Base on the improved
current-mode logic (ICML), the PLL can operates under 2~V and
the output frequency is up to 2~GHz. The total power
consumption of PLL is 88.25~mA. The macromodel of the PLL will
be introduced for simulation the lock process.
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