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Adiabatic Switching and Charge Recycling are two new techniques
to reduce power consumption: with the Adiabatic Switching
technique, heat dissipation on resistive device channels caused
by dynamic charging and discharging is reduced if energy
transfer period T >> RC, where RC is the time constant of the
circuit. Exploiting the Charge Recycling technique, loss of
stored energy in capacitive loads can be recovered for reuse in
subsequent cycles. In this paper, we propose a new logic family
- Pulsed Power Supply Cross-Coupled Differential Logic (PPS-
CCDL), which integrates the adiabatic differential logic gate
and a latch. PPS-CCDL can be shown througth derivations and
simulations to dissipate less power than the previously
proposed PPS-CMOS approach, by eliminating the PMOS trees and
the unnecessary signal glitches and transitions in PPS-CMOS. A
higher power saving of the overall system is anticipated since
PPS-CCDL presents a smaller and data-independent capacitive
loads to the pulsed power supply. We implemented an 8-bit
pipelined adder with a 0.8um standard CMOS technology, which is
under testing. Another application chip of PPS/static 23-bit
correlator with 8-bit I/O was submitted to CIC for fabrication.
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