臺灣博碩士論文加值系統

本篇論文主要探討路徑的真實性(path sensitizability)在邏輯線路
(logic circuit) 的效能最佳化(performance optimization)過程中的影
響，我們採用反復式的(iterative) 效能最佳化方式，在每一個效能最佳
化的┬步驟中，選擇一個閘(gate)並調整它的尺寸(gate resizing) 以降
低線路的時間延遲(circuit delay)， 這個步驟一直重複直到線路滿足時
效限制(timing constraint)。 因為只有真實路徑(sensitizable path)
能決定線路的時效，假性路徑(false path)必須被標示並排除，然而只在
一開始標示假性路徑並不恰當，因為在效能最佳化的過程中，假性路徑可
能變成真實路徑，而且，真實路徑也可能變成假性路徑，尤有甚者，某些
路徑可能很頻繁地在真實路徑和假性路徑間變換，也就是說會產生震盪的
現象。這種重要路徑 (critical path) 的震盪現象可能使得效能最佳化
的負擔加重，為了降低重要路徑的震盪現象，我們將提出一種較寬鬆(
loose) 的路徑真實性標準(sensitization criterion) 來同時標示真實
路徑與穿梭路徑(shuttle path)。然而路徑真實性標準的選擇必須與時效
限制的鬆緊度配合，因此，我們將定義一個路徑震盪係數(thrashing
coefficient) 以作為選擇路徑真實性標準的依據。隨著線路的運作速度
加快，耗能(power consumption) 變成設計線路時一個重要的考量，對於
一個已經滿足時效限制的線路，可以藉由縮小非重要路徑(non-critical
path) 上的元件之尺寸來降低耗能。在耗能的最佳化過程中，為了避免違
反已經滿足的時效限制，選擇具有時間延長容許(time slack)的閘來縮小
尺寸是可行的方法，基於對路徑的新分類方式(classification)，我們將
提出一種以路徑為導向的時間延長容許(time slack)計算方法，而且路徑
的真實性亦將被同時考慮進來。利用這個時間延長容許計算方法的結果，
我們將提出一個耗能最佳化的方法，其中，我們不僅考慮在非重要路徑上
降低耗能，在重要路徑上降低耗能的方法亦將被提出。

In an iterative performance optimization process, a circuit is
optimized by selecting a gate and replacing it by a faster one
iteratively until the performance requirements are met. Since
only sensitizable paths contribute to the delay of a circuit,
false paths must be excluded in optimizing the delay of the
circuit. However, just identifying sensitizable paths in the
first place is not sufficient since during optimization
process, false paths may become sensitizable, and sensitizable
paths false. In addition, some paths may shuttle frequently as
false paths and sensitizable ones. That is, a thrashing
phenomenon may occur. To lessen the thrashing phenomenon of
critical paths, a loose sensitization criterion will be
proposed in this dissertation to identify both exact
sensitizable paths and shuttle paths. Moreover, the selection
of sensitization criterion should be related to the specified
delay constraint of a given circuit. Taking into account the
tightness of sensitization criterion and delay constraint
together, we define in this dissertation a thrashing
coefficient which is used to guide the selection of
sensitization criterion in the performance optimization
process. The dissipated energy is increased as the chip
operates faster since the average power consumption of a
component is inversely proportional to the clock cycle time.
For a delay optimized circuit, the power consumption can be
reduced by down-sizing the gates on noncritical paths.
Selecting gates with time slack can be used to reduce the power
consumption of a circuit without violating the timing
constraint. Based on the new classification of path set made in
this dissertation, a path-oriented method in calculating slack
time with false path taken into consideration will be
developed. A power reduction algorithm will then be proposed
using the result of slack calculation procedure.

Cover
Contents
1 Introduction
2 Literature Review
2.1 Delay Optimization Considering Path Sensitizatoin
2.2 Minimizing the Power Dissipation of CMOS Combinational Circuit
2.3 Automatic Generation of Leaf-Cell Layout
3 Automatic Generation of Leaf-Cell with Timing Constraint
3.1 Abstract Model of a Template
3.2 Layout Generation of Leaf-Cell with Timing Constraint
3.3 Cell-Height Driven Transistor Sizing
3.3.1 Delay Graph Modeling
3.3.2 NLP Formulation
3.3.3 The Effectiveness of the NLP Formula
3.4 Timing Driven CMOS Cell Library Generation
3.4.1 Layout Style of the Cell Library
3.4.2 Automatic Generation of Leaf-Cell Layout
3.4.3 Characterization of Templates
3.5 Summary
4 Delay Optimization of Circuits Containing False Path
4.1 Cell-Based Delay Model
4.2 Path Sensitization
4.3 New Classification of Path Set
4.3.1 Conditions for False becoming Optimization Algorithm
4.3.2 Shuttle Paths
4.3.3 Function-false Paths
4.4 Sensitization Criteria in a Performance Optimization Algorithm
4.4.1 Sensitization Criteria
4.4.2 Thrashing Coefficient
4.4.3 Performance Optimization Algorithm
4.4.4 A Walk Through Example
4.5 Experimental Results
4.6 Summary
5 Power Reduction by Gate Sizing with Path-Oriented Slack Calculation
5.1 Introduction
5.2 Static Timing Analysis Underestimating Time Slack
5.3 Slack Calculation Taking Path Sensitizability into Account
5.3.1 Classification of Path Set
5.3.2 Path-Oriented Slack Calculation
5.4 Power Reduction by Iterative Gate Sizing
5.4.1 Power Estimation
5.4.2 Single Gate REsizing
5.4.3 Multiple Gates Resizing
5.4.4 Power Reduction Algorithm
5.5 Experimental Results
5.6 Summary
6 Conclusions and Future Work
Other