由於無線電通信和ULSI的應用,近年來相關的高速元件和IC引起了相
當的關注,而正能符合它的要求,不僅如此,SOI於Si IC之製造上也有多項
優點,如:製程簡化,封裝密度, 和抗高輻射....等
等.本論文首先就針對我們新發展的BESOI做一探討,而它主要的困難在於
達成低功率和高速元件所要求的低硼含量,對其主要的高溫過程磊晶和晶
片結合,我們分別以較低溫的800 oC和600 oC完成,這是目前BESOI最低溫
的製程,正如預期得到了最低殘留的硼含量. 本論文另一重要研究主
題,是改善少數載體元件的速度響應,其主要應用於切換二極體和積體光接
受器,我們使用離子佈植機將高濃度的Si植入Si晶片中,得到相當短的載子
生命週期,分別是植入後的1.2微微秒和400 oC退火後的1.9微微秒,並且發
現經過600 oC以上的高溫退火其少數載體的生命週期就超過了1毫微秒.再
加上對植入的濃度變化做比較,我們就其傳導機制做一探討.

High speed devices and integrated circuit have attracted
much attention recently , because of the application in wireless
communication and ULSI .Silicon-on-insulator(SOI) is necessary
to achieve this goal , and also has a lot of potential
advantages in Si device technology , i.e., process
simplification ,packing density , and radiation hardness . The
first part of this thesis is focused on our newly developed dond
and etch-back SOI(BESOI) . BESOI uses sub-u epitaxial Si
layers on heavily B-doped Si substrates and subsequently
bondedonto a Si wafer with a thermally grown oxide . An etch-
back process is followed to selectively remove the Si substrate
and the B-doped p+ layer . It is difficult to achive the fully
depleted MOSFET by conventional process with lower B
concentration , while it is essential to the low power andhigh
speed operation. We have used low temperature process in epitaxy
and wafer bonding . AbruptB profiles with concentration reduces
by three orders of magnitude within hundreds of A is achieved
for the Si epitaxial layer at a low growth temperatureof 800 oC.
A low bonding temperature of 600 oC with oxygen plasma activated
SiO2is obtained to achieve void-free wafer bonding . To date ,
our BESOI processes the lowest process temperature and the
residual B concentration measurement ison the way . Another
important research area is to improve the speed response in
minoritycarrier devices , which can be used in switching diodes
and integratedphoto-receiver . We have used the Si implanted Si
to study the carrier lifetime . Carrier lifetime of 1.2 and 1.9
ps are measured from the as-implanted and 400 oC annealed Si
respectively . The relative intensity of photoresponse is also
decreased by a factor of two after 400 oC annealing . In
contrast , therewere no measurable photoresponse up to 1 ns for
post-growth annealing above 600 oC . The increased carrier
lifetime after annealing is due to the reducedconcentration of
trap and recombination centers by the annealing effect .
Themeasured carrier lifetimes are also strongly related to the
sheet resistance . An eight fold increased sheet resistance
after 400 oC annealing may be due to the similar reduces hopping
conduction that observed in LT-GaAs . Furtherevidence can also
bemeasuredfrom more than two orders of reduced sheet resistance
as implanted dosage increased from 1E14 to 1E16 cm-2 , where the
concentrations ofdefects are increased with the increased
implanted dosage .