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研究生:賴宏光
研究生(外文):Lai, Horng-Goung
論文名稱:互補式金氧半低電壓法則型類比數位轉換器之分析及設計
論文名稱(外文):The Design and Analysis of Low-Voltage CMOS Algorithmic A/D Converter
指導教授:吳重雨, 呂平幸
指導教授(外文):Chung-Yu Wu, Ping-Hsing Lu
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1996
畢業學年度:84
語文別:中文
論文頁數:100
中文關鍵詞:低電壓類比數位轉換器
外文關鍵詞:Low VoltageA/D Converter
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當個人通訊時代的來臨,以及元件縮小化的趨勢;使得極大型積體電路(
ULSI)趨向低電壓工作特性。電源電壓將從5伏特到3伏特,再到2伏特,最
終至1伏特。不論是在數位或類比電路,特別是在超大型積體電路(VLSI)
混合式類比數位信號之處理都是不可避免的。這篇論文中提出一種在低電
壓創新於一般運算放大器之設計方法。利用此種技巧,設計且分析了一個
工作於1.2伏特與電容比例無關及對運算放大器的有限增益不敏感之法則
型類比數位轉換器。它包含了於低電壓下之運算放大器、比較器、閂鎖器
及開關提升器。此型式之類比數位轉換器具有對電容比值、運算放大器的
有限增益及偏離電壓不敏感之特性;因此主要誤差來自於開關的轉換。綜
上所述,此型式之類比數位轉換器極適合於低電壓的設計。根據理論所述
,一個利用0.8微米n-well互補式金氧半製程的實驗晶片已經設計並製造
出來,在8KHz取樣速度下,達到了8位元的解析度,而能量消耗為1.10mW
。量測出的結果顯示,此新型運算放大器具有50dB直流增益,2MHz單增益
頻率,50dB共模互斥比,以及2V/usec之延遲率。

The fast growing application of personal data processing and
communication systems as well as the inherent device
miniaturization has driven the CMOS ULSI ( Ultra Large Scale
Integrated circuit ) toward lower-voltage operation. The scaled-
down power supply voltages are from 5V, through 3.3V, toward 2V,
and ultimately to 1V. Under this scaling trend, both digital and
analog integrated circuits, particularly the mixed analog/
digital ULSI signal processing systems, should be designed by
using the low supply voltage as well as the submicron CMOS
devices.This thesis has proposed a new design technique to
design a low-voltage operational amplifier using the n-well PMOS
device with positive substrate bias. Using the proposed design
technique and the low-voltage CMOS Op Amp, a capacitor-ratio-
independent and gain-insensitive algorithmic analog-to-digital
converter at 1.2V power supply voltage is analyzed and designed.
It consists of operational amplifiers, comparators, latch, and
clock booster which have been designed associated with the novel
techniques for low supply-voltage operation. The configuration
of this algorithmic analog-to-digital converter is inherently
insensitive to capacitor ratio accuracy as well as the finite
gain and the offset voltage of the operational amplifiers.
Therefore, the switching error is the major error source. With
fully differential configuration, it is suitable for 1.2V low
voltage operation. The simulated results have shown that this
algorithmic A/D converter can achieve 8 bit resolution at 1.2V
supply voltage with 1.10mW power consumption. Furthermore, the
proposed Op Amp and A/D converter have been fabricated with the
0.8(m n-well DPDM CMOS process with doubled poly linear
capacitor. The experimental result shows that the proposed Op
Amp has a dc gain of 50dB, unity-gain frequency of 2MHz, CMRR
about 50dB and slew rate is 2V/(sec.

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