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研究生:鄭基廷
研究生(外文):Cheng, Chi-Ting
論文名稱:供電路模擬器SPICE使用之複晶矽薄膜電晶體模式
論文名稱(外文):A Physically-Based Model of Poly-Silicon Thin Film Transistors for SPICE
指導教授:莊紹勳
指導教授(外文):Steve S. Chung
學位類別:碩士
校院名稱:國立交通大學
系所名稱:電子研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1996
畢業學年度:84
語文別:中文
論文頁數:71
中文關鍵詞:複晶矽薄膜電晶體電流電壓模式電容電壓模式電路模擬器可靠性
外文關鍵詞:Poly-Silicon Thin Film TransistorI-V modelC-V modelSPICEReliability
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最近,複晶矽薄膜電晶體由於其廣泛的應用在平面顯示器及三度空間
積體電路上而受到廣泛的注意。傳統上,複晶矽薄膜電晶體有一絕緣基板
及大約12伏特的操作電壓,同時其電特性和複晶矽材料的特性也有極大的
關連。所以,我們不能以傳統的MOS電晶體元件模式來描述複晶矽薄膜電晶
體元件的操作。到目前為止,很少研究是針對複晶矽薄膜電晶體的元件模
式,特別是以發展在SPICE電路模擬器上的I-V及C-V模式更是付之闕如。所
以本研究的目的就是發展在SPICE上用來設計電路的元件模式。本論文嘗
試發展一套以物理為基礎的的複晶矽薄膜電晶體I-V及C-V模式。首先,必
須發展一套複晶矽薄膜電晶體的元件模式以及其中參數的粹取方式,參數
粹取主要由實驗資料而得,得到之後再帶回所發展的模式中驗證其正確性
。所引用的實驗數據主要為一上閘極的TFT元件結構,閘極氧化層厚度約
為60nm,通道長度從5mm到10mm,且是低溫製程。經由上述步驟所得到的模
式已放入SPICE電路模擬器中從而預測及分析複晶矽薄膜電晶體的電路特
性,如環型振盪器及類比放大器等。複晶矽薄膜電晶體尚有一非常重要的
課題,那就是其可靠性的分析。由於複晶矽材料有許多缺陷在其晶界處,我
們通常會在元件製作完成後用氫化來提升元件的特性,但此步驟在長期電
的應力下對元件特性會造成不穩定。藉由一些電的可靠性分析,我們可以
進一步探討其不穩定的機制,例如氫鍵的斷裂或是載子的捕捉等。在本次
論文的最後,我們探討複晶矽薄膜電晶體的可靠性,分析其理由,並加以模
式化,以期有效及正確的模擬複晶矽薄膜電晶體不穩定的元件特性。

Recently, poly-silicon Thin Film Transistors(poly-Si TFT's)
have been extensively studied because of their important
applications in flat-panel display and three-dimentional
integration. Typically, TFT operates with a floating substrate
and the operation bias is about 12V. Moreover, the
characteristics of aTFT cannot be accurately modeled by the
common bulk MOSFET model in SPICE. As poly-Si TFTs technology
matures and more complex analog and digital circuits become
feasible, the lack of an accurate circuit model will be the
major factor limiting circuit integration. It is, therefore,
essential to establish a precise poly-Si TFTs circuit model,
suitable for use in circuit simulations. This work
attempts to develop a physically-based analytical current-
voltage model and an intrinsic capacitance-voltage model of ply-
Si TFTs for circuit simulation. First, we have developed a set
of programs including I-V and C-V models and parameter
extraction methods. The model parameters are extracted from the
experimental data and then substituted back into the developed
models. The accuracy of these models are verified as compared
with experimental data. Then, both models were successfully
implenmented in SPICE. The experiment data used here are
measured from a LCD wafer with p-substrate and top-gate
structure. The gate oxide thickness is 60nm. The channel length
ranges from 5um to 10um. these device models are finally
implemented in the SPICE circuit simulator(version 2G.6)to
predict and analyze the circuit performance of poly-Si TFTs such
as ring oscillator, amplifier, etc.
Device reliability issues are also important in the poly-Si TFTs
due to theimperfection properties in the polysilicon crystals.
It exhibits many defects throughout the material, espically at
the grain-boundary. The general method improving device
performance is to post-process the TFT's with hydrogen plasma
passivation. The method improves device performance but is
unstable under long term electrical stress. By using bias and
temperature stress at the poly-Si TFTs, it is possible to
explore mechanisms of the unstable phenomena such as break of
hydrogn bounds, carrier traping, etc. In the final part of the
work, we try to find the reasons of device degradation by
realizating some stress experiments.

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