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研究生:游志成
研究生(外文):You, Jyh Cheng
論文名稱:光二極體與電荷耦合元件間連結區域之電性分析
論文名稱(外文):Analysis no the Electrical Properties of the Linking Area between Photodiodes and Charge Coupled Devices
指導教授:龔正龔正引用關係
指導教授(外文):Gong Jeng
學位類別:碩士
校院名稱:國立清華大學
系所名稱:電機工程研究所
學門:工程學門
學類:電資工程學類
論文種類:學術論文
論文出版年:1996
畢業學年度:84
語文別:英文
論文頁數:56
中文關鍵詞:傳輸障礙電荷耦合元件傳輸損失
外文關鍵詞:transfer barriersmall wellCCD
相關次數:
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在本論文中,我們利用Tsuprem4和Medici軟體去建立一個完整的流程,詳細
地去分析光二極體與電荷耦合元件間連結區域的電性及傳輸特性;其分析
著重於小位能井障礙,讀取方式,讀取電壓,還有本體和界面缺陷.在電壓波
形方面,利用真實的輸入電壓實際去模擬整個暫態分析;利用設定電子準費
米電位來空乏之前儲存在位能井中的電子.我們模擬分析了光二極體與電
荷耦合元件間傳送的效率和電子在儲存於電荷耦合元件期間,受本體與界
面缺陷的影響.透過整個分析與模擬,我們可以找出在何種條件下的結構才
是最好的設計.在傳送訊號的過程中,光二極體與電荷耦合元件間連結區域
形成一小位能井障礙,由於它阻擋了許多電子的傳輸,造成傳輸效率的低
落,並大大地影響了此結構的實用性.我們發現,增加電荷耦合元件的濃度,
降低光二極體n-型的濃度和縮短傳送路徑,都將有利於電荷的傳送.雖然增
加電荷耦合元件濃度,不但有利於電荷的傳送,且增加了最大電荷載子容
量,但卻嚴重了本體結合效應.降低了光二極體n-型的濃度,卻又降低了光
二極體的最大載子容量.若是結構已被固定,增加讀取電壓將會減少傳輸損
失.在本體缺陷方面,我們發現,較少的缺陷密度,較長的缺陷時間常數和缺
陷能量較靠近導通帶,都有助於減少電荷的損失.但缺陷時間常數通常與缺
陷能量的位置息息相關,更增加了其複雜度.至於在界面缺陷方面,雖然界
面缺陷有助於電荷的傳送,但卻增加了電荷被捕捉的機率.

In this thesis, the electrical properties of the linking area
between photodiodes ans charge coupled devices are analyzed
based on the considerations of the formation of a small well,
read-out through surface channel, read-out by punchthrough
mechanism, read -out pulse, and bulk and interface traps. An
electron quasi-fermi potential is set to deplete initial
storage wells under transient analysis. Through this transient
simulation, we calculated the charge loss in different
conditions during charge transfer periods. The process
simulation was built such that through Tsuprem4 and
Medici simulations we can construct a whole procedure
for charge transfer. This prediction is important, because
we can decide a better structure with less time and less
silicon try out. The transfer loss due to a small well barrier
existed between the photodiode and the CCD is particularly
studied. The transfer loss is reduced, even approaching zero,
when the CCD peak doping becomes heavier and the n-diode region
of the photodiode beneath interface becomes narrower or doped
lighter. If a structure is given, this small barrier can
also be reduced by increasing the gate voltage. After charges
having been transferred into CCDs, the bulk and interface traps
become affecting. The devices will be benefited if the bulk
trap has fewer trap density, longer trap lifetime,and with
electron traps closer to conduction band. As to interface
traps, although the n-type acceptor-like traps at interface
is good for transfer, they also cause more serious charge loss.

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