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A multiplexer is used to achieve simultaneous transmission of
multiple low rate tributaries over a single high speed carrier.
The MX3 Multiplexer multiplexes 21 E1 or 28 DS1 signals into a
DS3 signal. The designed MX3 system is a multi-board
multiprocessor-based system. System firmware and board-level
firmware are needed to perform monitor and control functions for
the system.The system control unit (SCU) is equipped in each MX3
Multiplexer, which consists of MC68302 integrated multi-protocol
processor, memories and FPGA-implemented I/O ports. The 8051
microprocessor is equipped in each transmission-related units
and power units. The system management is achieved by the inter-
board communications among those microprocessors, i.e., MC68302
and 8051 microprocessors.The hardware design and the firmware of
the SCU, the firmware of the on-board 8051s and the inter-
processor communication protocol are developed and implemented
in this thesis.
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