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A real-time high-speed double-error-correcting binary BC decoder is implemented in the thesis. The modified step-by-step method was adopted in the design for avoiding the task of finding error location polynomial and inverse operations. The presented decoder consists of syndrome module, comparison module, and corrector module. To obtain a high-speed decoding speed, linear systolic architecture combined with systolic circuits employed. In addition, software simulation with C-language and hardware simulation with Verilog-XL are used to check each other. Based on the simulations and proposed architecture, a cellhused chip of the decoder is then implemented.
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